XC4062XL-2BG432C Xilinx Inc, XC4062XL-2BG432C Datasheet - Page 22
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XC4062XL-2BG432C
Manufacturer Part Number
XC4062XL-2BG432C
Description
IC FPGA C-TEMP 3.3V 2SPD 432MBGA
Manufacturer
Xilinx Inc
Series
XC4000E/Xr
Datasheet
1.XC4005E-4PC84C.pdf
(68 pages)
Specifications of XC4062XL-2BG432C
Number Of Logic Elements/cells
5472
Number Of Labs/clbs
2304
Total Ram Bits
73728
Number Of I /o
352
Number Of Gates
62000
Voltage - Supply
3 V ~ 3.6 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
432-LBGA, Metal
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XC4062XL-2BG432C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
XC4000E and XC4000X Series Field Programmable Gate Arrays
or clear on reset and after configuration. Other than the glo-
bal GSR net, no user-controlled set/reset signal is available
to the I/O flip-flops. The choice of set or clear applies to
both the initial state of the flip-flop and the response to the
Global Set/Reset pulse. See
page 11
JTAG Support
Embedded logic attached to the IOBs contains test struc-
tures compatible with IEEE Standard 1149.1 for boundary
scan testing, permitting easy chip and board-level testing.
More information is provided in
page
Three-State Buffers
A pair of 3-state buffers is associated with each CLB in the
array. (See
can be used to drive signals onto the nearest horizontal
longlines above and below the CLB. They can therefore be
used to implement multiplexed or bidirectional buses on the
horizontal longlines, saving logic resources. Programmable
pull-up resistors attached to these longlines help to imple-
ment a wide wired-AND function.
The buffer enable is an active-High 3-state (i.e. an
active-Low enable), as shown in
Another 3-state buffer with similar access is located near
each I/O block along the right and left edges of the array.
(See
The horizontal longlines driven by the 3-state buffers have
a weak keeper at each end. This circuit prevents undefined
floating levels. However, it is overridden by any driver, even
a pull-up resistor.
Special longlines running along the perimeter of the array
can be used to wire-AND signals coming from nearby IOBs
or from internal longlines. These longlines form the wide
edge decoders discussed in
page
Three-State Buffer Modes
The 3-state buffers can be configured in three modes:
• Standard 3-state buffer
• Wired-AND with input on the I pin
• Wired OR-AND
6-26
Figure 21: Open-Drain Buffers Implement a Wired-AND Function
Figure 33 on page
42.
27.
for a description of how to use GSR.
Figure 27 on page
D
A
WAND1
34.)
Product Obsolete or Under Obsolescence
“Wide Edge Decoders” on
30.) These 3-state buffers
Table
“Global Set/Reset” on
“Boundary Scan” on
D
B
13.
WAND1
Z = D
D
D
C
D
A
D
Standard 3-State Buffer
All three pins are used. Place the library element BUFT.
Connect the input to the I pin and the output to the O pin.
The T pin is an active-High 3-state (i.e. an active-Low
enable). Tie the T pin to Ground to implement a standard
buffer.
Wired-AND with Input on the I Pin
The buffer can be used as a Wired-AND. Use the WAND1
library symbol, which is essentially an open-drain buffer.
WAND4, WAND8, and WAND16 are also available. See the
XACT Libraries Guide for further information.
The T pin is internally tied to the I pin. Connect the input to
the I pin and the output to the O pin. Connect the outputs of
all the WAND1s together and attach a PULLUP symbol.
Wired OR-AND
The buffer can be configured as a Wired OR-AND. A High
level on either input turns off the output. Use the
WOR2AND library symbol, which is essentially an
open-drain 2-input OR gate. The two input pins are func-
tionally equivalent. Attach the two inputs to the I0 and I1
pins and tie the output to the O pin. Tie the outputs of all the
WOR2ANDs together and attach a PULLUP symbol.
Three-State Buffer Examples
Figure 21
ment a wired-AND function. When all the buffer inputs are
High, the pull-up resistor(s) provide the High output.
Figure 22
ment a multiplexer. The selection is accomplished by the
buffer 3-state signal.
Pay particular attention to the polarity of the T pin when
using these buffers in a design. Active-High 3-state (T) is
identical to an active-Low output enable, as shown in
Table
Table 13: Three-State Buffer Functionality
WOR2AND
B
(D
C
+D
13.
D
) (D
IN
IN
X
E
shows how to use the 3-state buffers to imple-
shows how to use the 3-state buffers to imple-
+D
F
)
D
D
E
F
WOR2AND
T
1
0
May 14, 1999 (Version 1.6)
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X6465
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P
OUT
IN
Z
R