XCS30-3VQ100C Xilinx Inc, XCS30-3VQ100C Datasheet
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XCS30-3VQ100C
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XCS30-3VQ100C Summary of contents
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... Device Cells XCS05 and XCS05XL 238 XCS10 and XCS10XL 466 10,000 XCS20 and XCS20XL 950 20,000 XCS30 and XCS30XL 1368 30,000 XCS40 and XCS40XL 1862 40,000 Notes: 1. Max values of Typical Gate Range include 20-30% of CLBs used as RAM. 2. XCS40XL provided 224 max I/O in CS280 package discontinued by PDN2004-01. ...
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Spartan and Spartan-XL FPGA Families Data Sheet General Overview Spartan series FPGAs are implemented with a regular, flex- ible, programmable architecture of Configurable Logic Blocks (CLBs), interconnected by a powerful hierarchy of versatile routing resources (routing channels), and sur- rounded ...
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R Spartan and Spartan-XL devices provide system clock rates exceeding 80 MHz and internal performance in excess of 150 MHz. In addition to the conventional benefit of high volume programmable logic solutions, Spartan series FPGAs also offer on-chip edge-triggered single-port ...
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Spartan and Spartan-XL FPGA Families Data Sheet G-LUT G4 G4 Logic G3 G3 Function G1- DIN F4 F4 Logic F3 F3 Function F1- F-LUT K EC ...
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R . Table 2: CLB Storage Element Functionality Mode CK EC Power- GSR Flip-Flop X X Operation Latch 1 1* Operation 0 1* (Spartan-XL) Both X 0 Legend: X Don’t care Rising edge (clock ...
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Spartan and Spartan-XL FPGA Families Data Sheet Multiplexer Controlled by Configuration Program Figure 4: CLB Control Signal Interface The four internal control signals are: • EC: Enable Clock • SR: Asynchronous Set/Reset or H function generator ...
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R The register choice is made by placing the appropriate library symbol. For example, IFD is the basic input flip-flop (rising edge triggered), and ILD is the basic input latch (transparent-High). Variations with inverted clocks are also available. The clock ...
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Spartan and Spartan-XL FPGA Families Data Sheet Table 4: Supported Sources for Spartan/XL Inputs Spartan Inputs 5V, Source TTL √ Any device 3.3V, CC CMOS outputs √ Spartan family 5V, CC TTL outputs √ Any device, ...
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R Output Multiplexer/2-Input Function Generator (Spartan-XL Family Only) The output path in the Spartan-XL family IOB contains an additional multiplexer not available in the Spartan family IOB. The multiplexer can also be configured as a 2-input function generator, implementing a ...
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Spartan and Spartan-XL FPGA Families Data Sheet This high value makes them unsuitable as wired-AND pull-up resistors. Table 7: Supported Destinations for Spartan/XL Outputs Spartan-XL Outputs Destination 3.3V, CMOS √ Any device 3.3V, CC CMOS-threshold inputs √ Any ...
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R PSM PSM 2 Doubles Figure 8: Spartan/XL CLB Routing Channels and Interface Block Diagram CLB Interface A block diagram of the CLB interface signals is shown in Figure 9. The input signals to the CLB are distributed evenly on ...
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Spartan and Spartan-XL FPGA Families Data Sheet Double-Length Lines The double-length lines consist of a grid of metal segments, each twice as long as the single-length lines: they run past two CLBs before entering a PSM. Double-length lines are grouped ...
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R BUFGS PGCK1 SGCK1 BUFGP 4 IOB locals Any BUFGS X4 locals One BUFGP per Global Line IOB BUFGS PGCK2 SGCK2 BUFGP Figure 11: 5V Spartan Family Global Net Distribution The four Primary Global buffers offer the shortest delay and ...
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Spartan and Spartan-XL FPGA Families Data Sheet • The single-port configuration contains a RAM array with 16 locations, each one-bit wide. One 4-bit address decoder determines the RAM location for write and read operations. There is one ...
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R WCLK (K) T WSS WE T DSS DATA IN T ASS ADDRESS T ILO DATA OUT Figure 13: Data Write and Access Timing for RAM WCLK can be configured as active on either the rising edge (default) or the ...
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Spartan and Spartan-XL FPGA Families Data Sheet CLB signals from which they are originally derived are shown in Table 10. Table 10: Dual-Port RAM Signals RAM Signal Function D Data In A[3:0] Read Address for Single-Port. Write Address for Single-Port ...
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R and Spartan-XL families, speeding up arithmetic and count- ing functions. The carry chain in 5V Spartan devices can run either up or down. At the top and bottom of the columns where there are no CLBs above and below, ...
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Spartan and Spartan-XL FPGA Families Data Sheet C OUT CARRY LOGIC G CARRY OUT0 H1 F CARRY Figure 16: Fast Carry Logic in Spartan/XL CLB www.xilinx.com ...
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Figure 17: Detail of Spartan/XL Dedicated Carry Logic 3-State Long Line Drivers A pair of 3-state buffers is associated with each CLB in the array. These 3-state buffers (BUFT) ...
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Spartan and Spartan-XL FPGA Families Data Sheet On-Chip Oscillator Spartan/XL devices include an internal oscillator. This oscil- lator is used to clock the power-on time-out, for configura- tion memory clearing, and as the source of CCLK in Master configuration mode. ...
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R Figure diagram of the Spartan/XL FPGA boundary scan logic. It includes three bits of Data Register per IOB, the IEEE 1149.1 Test Access Port controller, and the Instruction Register with decodes. Spartan/XL devices can also be ...
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Spartan and Spartan-XL FPGA Families Data Sheet IOB IOB IOB IOB IOB IOB IOB IOB IOB IOB IOB BYPASS REGISTER INSTRUCTION REGISTER TDI 22 DATA IN IOB.T IOB IOB IOB IOB IOB.I IOB IOB IOB IOB.Q IOB IOB.T M TDO ...
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R Table 12: Boundary Scan Instructions Instruction Test Selected EXTEST SAMPLE/ PRELOAD USER USER READBACK CONFIGURE 1 ...
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... Spartan-XL family the die version number Table 13: IDCODEs Assigned to Spartan-XL FPGAs FPGA XCS05XL XCS10XL XCS20XL XCS30XL XCS40XL 24 Configuration State: The configuration state is available to JTAG controllers. Configuration Disable: The JTAG port can be prevented from configuring the FPGA. ...
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R PWRDWN Outputs Power-down retains the configuration, but loses all data stored in the device flip-flops. All inputs are interpreted as Low, but the internal combinatorial logic is fully functional. Make sure that the combination of all inputs Low and ...
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Spartan and Spartan-XL FPGA Families Data Sheet During configuration, some of the I/O pins are used tempo- rarily for the configuration process. All pins used during con- figuration are shown in Table 14 and Table 14: Pin Functions During Configuration ...
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R Master Serial Mode The Master serial mode uses an internal oscillator to gener- ate a Configuration Clock (CCLK) for driving potential slave devices and the Xilinx serial-configuration (SPROM). The CCLK speed is selectable as either 1 MHz (default) or ...
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Spartan and Spartan-XL FPGA Families Data Sheet Slave Serial is the default mode if the Mode pins are left unconnected, as they have weak pull-up resistors during configuration. Multiple slave devices with identical configurations can be wired with parallel DIN ...
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R DIN T DCC CCLK DOUT (Output) Symbol T DCC T CCD T CCO T CCH T CCL F CC Notes: 1. Configuration must be delayed until the INIT pins of all daisy-chained FPGAs are High. Figure 26: Slave Serial ...
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Spartan and Spartan-XL FPGA Families Data Sheet to the DONE pin. User I/Os for each device become active after the DONE pin for that device goes High. (The exact timing is determined by development system options.) Since the DONE pin ...
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R CCLK T IC INIT D0-D7 DOUT Symbol CCLK T CCH T CCL F CC Notes: If not driven by the preceding DOUT, CS1 must remain High until the 1. device is fully configured. ...
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Spartan and Spartan-XL FPGA Families Data Sheet Table 16: Spartan/XL Data Stream Formats Serial Modes Data Type (D0...) Fill Byte 11111111b Preamble Code 0010b Length Count COUNT[23:0] Fill Bits 1111b Field Check - Code Start Field 0b Data Frame DATA[n–1:0] ...
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... However, the Length Count value must be adjusted for all such extra "one" bits, even for extra leading ones at the beginning of the header. 3. Express mode adds 57 (XCS05XL, XCS10XL (XCS20XL, XCS30XL, XCS40XL) bits per frame, + additional start-up bits. 4. XCS40XL provided 224 max I/O in CS280 package discontinued by PDN2004-01. ...
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Spartan and Spartan-XL FPGA Families Data Sheet LAST DATA FRAME Configuration Sequence There are four major steps in the Spartan/XL FPGA power-up configuration sequence. • Configuration Memory Clear • Initialization • Configuration • Start-up ...
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Boundary Scan Valid Instructions Available: Yes Test MODE, Generate One Time-Out Pulse Keep Clearing Configuration Memory EXTEST* SAMPLE/PRELOAD Completely Clear BYPASS Configuration Memory CONFIGURE* Once More (* if PROGRAM = High) ...
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Spartan and Spartan-XL FPGA Families Data Sheet to wait after completing the configuration memory clear operation. When INIT is no longer held Low externally, the device determines its configuration mode by capturing the state of the Mode pins, and is ...
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R Length Count Match CCLK DONE I/O CCLK_NOSYNC GSR Active DONE I/O CCLK_SYNC GSR Active DONE I/O UCLK_NOSYNC GSR Active DONE I/O UCLK_SYNC GSR Active Synchronization Uncertainty Configuration Through the Boundary Scan Pins Spartan/XL devices can be configured through the ...
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Spartan and Spartan-XL FPGA Families Data Sheet Readback The user can read back the content of configuration mem- ory and the level of certain internal nodes without interfering with the normal operation of the device. Readback not only reports the ...
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R Readback Abort When the Readback Abort option is selected, a High-to-Low transition on RDBK.TRIG terminates the Readback opera- tion and prepares the logic to accept another trigger. After an aborted Readback, additional clocks (up to one Readback clock per ...
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Spartan and Spartan-XL FPGA Families Data Sheet Readback Switching Characteristics Guidelines The following guidelines reflect worst-case values over the recommended operating conditions. Finished Internal Net rdbk.TRIG T RTRC rdclk.I T RCL rdbk.RIP rdbk.DATA DUMMY Figure 33: Spartan and Spartan-XL Readback ...
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R Configuration Switching Characteristics PROGRAM INIT CCLK Output or Input Master Mode Symbol Description T Power-on reset POR T Program Latency PI T CCLK (output) delay ICCK T CCLK (output) period, slow CCLK T CCLK (output) period, ...
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Spartan and Spartan-XL FPGA Families Data Sheet Spartan Family Detailed Specifications Definition of Terms In the following tables, some specifications may be designated as Advance or Preliminary. These terms are defined as follows: Advance: Initial estimates based on simulation and/or ...
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... GND, and the FPGA configured with a Tie CC Speed Grade -4 -3 Device Max Max XCS05 2.0 4.0 XCS10 2.4 4.3 XCS20 2.8 5.4 XCS30 3.2 5.8 XCS40 3.5 6.4 XCS05 2.5 4.4 XCS10 2.9 4.7 XCS20 3.3 5.8 XCS30 3.6 6.2 XCS40 3.9 6.7 Units - μ Units ...
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Spartan and Spartan-XL FPGA Families Data Sheet Spartan Family CLB Switching Characteristic Guidelines All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test pat- terns. Listed below are representative values. For more specific, more precise, ...
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R Spartan Family CLB RAM Synchronous (Edge-Triggered) Write Operation Guidelines All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test pat- terns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed ...
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Spartan and Spartan-XL FPGA Families Data Sheet Spartan Family CLB RAM Synchronous (Edge-Triggered) Write Operation Guidelines (continued) All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test pat- terns. Listed below are representative values. For ...
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... XCS05 5.8 9.2 XCS10 6.2 9.6 XCS20 6.6 9.8 XCS30 7.0 9.9 XCS40 7.3 10.7 XCS05 9.5 12.0 XCS10 9.9 12.5 XCS20 10.3 12.7 XCS30 10.7 13.2 XCS40 11.0 14.3 All devices 0.8 1.0 All devices 1.5 2.0 Figure 33. Units ...
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Spartan and Spartan-XL FPGA Families Data Sheet Capacitive Load Factor Figure 33 shows the relationship between I/O output delay and load capacitance. It allows a user to adjust the specified output delay if the load capacitance is different than 50 ...
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... XCS20 0.5 / 3.2 0.9 / 4.5 XCS30 0.3 / 3.5 0.6 / 5.0 XCS40 0.1 / 4.0 0.3 / 5.7 XCS05 4.0 / 0.0 5.7 / 0.0 XCS10 4.0 / 0.0 5.7 / 0.0 XCS20 4.0 / 0.5 5.7 / 0.5 XCS30 4.0 / 0.5 5.7 / 0.5 XCS40 5.0 / 0.0 6.5 / 0.0 Units ...
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... All devices 0.0 All devices - All devices - All devices - All devices - XCS05 3.6 XCS10 3.7 XCS20 3.8 XCS30 4.5 XCS40 5.5 All devices 11.5 XCS05 - XCS10 - XCS20 - XCS30 - XCS40 - www.xilinx.com R Speed Grade -4 -3 Max Min Max Units - ...
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... All devices All devices All devices All devices All devices All devices All devices All devices XCS05 XCS10 XCS20 XCS30 XCS40 threshold, with 50 pF external capacitive loads including test fixture. Slew-rate limited output CC www.xilinx.com Speed Grade -4 -3 Min Max Min Max Units 3 ...
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Spartan and Spartan-XL FPGA Families Data Sheet Spartan-XL Family Detailed Specifications Definition of Terms In the following tables, some specifications may be designated as Advance or Preliminary. These terms are defined as follows: Advance: Initial estimates based on simulation and/or ...
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R Spartan-XL Family DC Characteristics Over Operating Conditions Symbol V High-level output voltage @ I OH High-level output voltage @ I V Low-level output voltage @ I OL Low-level output voltage @ I Low-level output voltage @ I V Data ...
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... Description www.xilinx.com Speed Grade -5 -4 Device Max Max XCS05XL 1.4 1.5 XCS10XL 1.7 1.8 XCS20XL 2.0 2.1 XCS30XL 2.3 2.5 XCS40XL 2.6 2.8 DS060 (v1.8) June 26, 2008 Product Specification R Units ...
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R Spartan-XL Family CLB Switching Characteristic Guidelines All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test pat- terns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the ...
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Spartan and Spartan-XL FPGA Families Data Sheet Spartan-XL Family CLB RAM Synchronous (Edge-Triggered) Write Operation Guidelines All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test pat- terns. Listed below are representative values. For more ...
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R Spartan-XL Family CLB RAM Synchronous (Edge-Triggered) Write Operation Guidelines (cont.) All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test pat- terns. Listed below are representative values. For more specific, more precise, and worst-case ...
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... Description threshold with 50 pF external capacitive load. CC www.xilinx.com Speed Grade -5 -4 Device Max Max XCS05XL 4.6 5.2 XCS10XL 4.9 5.5 XCS20XL 5.2 5.8 XCS30XL 5.5 6.2 XCS40XL 5.8 6.5 All Devices 1.5 1.7 DS060 (v1.8) June 26, 2008 Product Specification R Units ...
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... Listed below are representative values for typical pin loca- tions and normal clock loading. Description XCS05XL XCS10XL XCS20XL XCS30XL XCS40XL XCS05XL XCS10XL XCS20XL XCS30XL XCS40XL Figure 35: Delay Factor at Various Capacitive Loads www.xilinx.com Speed Grade ...
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... All devices 0.0 All devices - All devices - All devices - All devices - XCS05XL 4.0 XCS10XL 4.8 XCS20XL 5.0 XCS30XL 5.5 XCS40XL 6.5 All devices 10.5 XCS05XL - XCS10XL - XCS20XL - XCS30XL - XCS40XL - www.xilinx.com R Speed Grade -5 -4 Max Min Max Units - ...
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... All devices All devices All devices All devices All devices All devices All devices All devices XCS05XL XCS10XL XCS20XL XCS30XL XCS40XL threshold, with 50 pF external capacitive loads including test fixture. Slew-rate limited output CC www.xilinx.com Speed Grade -5 -4 Min Max Min Max ...
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Spartan and Spartan-XL FPGA Families Data Sheet Pin Descriptions There are three types of pins in the Spartan/XL devices: • Permanently dedicated pins • User I/O pins that can have special functions • Unrestricted user-programmable I/O pins. Before and during ...
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R Table 18: Pin Descriptions (Continued) I/O During I/O After Pin Name Config. Config. PWRDWN I I User I/O Pins That Can Have Special Functions TDO O O TDI, TCK, I I/O TMS or I (JTAG) HDC O I/O LDC ...
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Spartan and Spartan-XL FPGA Families Data Sheet Table 18: Pin Descriptions (Continued) I/O During I/O After Pin Name Config. Config. SGCK1 - Weak I or I/O SGCK4 Pull-up (Spartan) (except SGCK4 is DOUT) GCK1 - Weak I or I/O GCK8 ...
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R Device-Specific Pinout Tables Device-specific tables include all packages for each Spar- tan and Spartan-XL device. They follow the pad locations around the die, and include boundary scan register loca- tions. Some Spartan-XL devices are available in Pb-free package options. ...
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Spartan and Spartan-XL FPGA Families Data Sheet XCS05 and XCS05XL Device Pinouts XCS05/XL Pad Name PC84 I/O P70 (2) I/O (D0 , DIN) P71 (1) (2) I/O, SGCK4 , GCK6 P72 (DOUT) CCLK P73 VCC P74 O, TDO P75 GND ...
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R XCS10 and XCS10XL Device Pinouts XCS10/XL (4) Pad Name PC84 VQ100 CS144 VCC P33 P25 Not P34 P26 Connect- ( PWRDWN ) I/O, P35 P27 (1) PGCK2 (2) GCK3 I/O (HDC) P36 P28 I I/O ...
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Spartan and Spartan-XL FPGA Families Data Sheet XCS10 and XCS10XL Device Pinouts XCS10/XL (4) Pad Name PC84 VQ100 CS144 I/O P80 P81 A10 GND - - I I I/O P81 P82 I/O P82 P83 I/O - ...
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R XCS20 and XCS20XL Device Pinouts XCS20/XL (2,4) Pad Name VQ100 CS144 TQ144 I/O P10 F1 GND P11 G2 VCC P12 G1 I/O P13 G3 I/O P14 G4 I/O P15 H1 ...
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Spartan and Spartan-XL FPGA Families Data Sheet XCS20 and XCS20XL Device Pinouts XCS20/XL (2,4) Pad Name VQ100 CS144 TQ144 PROGRAM P52 M13 (2) I/O (D7 ) P53 L12 I/O, P54 L13 (1) PGCK3 , (2) GCK5 I/O - K10 I/O ...
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... The “PWRDWN” on the XCS20XL is not part of the Boundary Scan chain. For the XCS20XL, subtract 1 from all Boundary Scan numbers from GCK3 on (247 and higher). 4. CS144 package discontinued by PDN2004-01 XCS30 and XCS30XL Device Pinouts XCS30/XL (5) Pad Name VQ100 VCC P89 I/O ...
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... Spartan and Spartan-XL FPGA Families Data Sheet XCS30 and XCS30XL Device Pinouts (Continued) XCS30/XL (5) Pad Name VQ100 I/O - I/O, TDI P4 I/O, TCK P5 I/O - I/O - I/O - I/O - I/O - I/O - GND - I/O - I/O - I/O, TMS P6 I/O P7 VCC - I/O - I/O - I/O - I/O - I/O - I/O ...
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... R XCS30 and XCS30XL Device Pinouts (Continued) XCS30/XL (5) Pad Name VQ100 I/O P18 I/O P19 I/O - I/O - I/O P20 (1) (2) I/O, SGCK2 , GCK2 P21 (1) (2) Not Connected , M1 P22 GND P23 (1) (2) MODE , M0 P24 VCC P25 (1) Not Connected , P26 (2) PWRDWN (1) (2) I/O, PGCK2 ...
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... Spartan and Spartan-XL FPGA Families Data Sheet XCS30 and XCS30XL Device Pinouts (Continued) XCS30/XL (5) Pad Name VQ100 I/O - I/O - I/O - VCC - I/O P43 I/O P44 I/O - I/O - GND - I/O - I/O - I/O - I/O - I/O - I/O - I/O P45 I/O P46 I/O - I/O - I/O ...
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... R XCS30 and XCS30XL Device Pinouts (Continued) XCS30/XL (5) Pad Name VQ100 I/O - I/O - I/O P59 I/O P60 (2) I/O (D4 ) P61 I/O P62 VCC P63 GND P64 (2) I/O (D3 ) P65 I/O P66 I/O P67 I/O - I/O - I/O - (2) I/O (D2 ) P68 I/O P69 VCC - I/O - I/O - I/O ...
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... Notes Spartan family only 2. 3V Spartan-XL family only 3. The “PWRDWN” on the XCS30XL is not part of the Boundary Scan chain. For the XCS30XL, subtract 1 from all Boundary Scan numbers from GCK3 on (295 and higher). (4) (4) 4. Pads labeled GND or V are internally bonded to Ground ...
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R CS280 VCC Pins E13 G5 G15 H5 J15 L5 L15 M5 N15 R13 - - - Not Connected Pins A4 A12 C8 C12 D17 H2 H3 H18 H19 M16 ...
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Spartan and Spartan-XL FPGA Families Data Sheet XCS40 and XCS40XL Device Pinouts XCS40/XL Pad Name PQ208 PQ240 BG256 CS280 GND P25 P29 GND VCC P26 P30 VCC I/O P27 P31 L2 I/O P28 P32 L3 I/O P29 P33 L4 I/O ...
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R XCS40 and XCS40XL Device Pinouts XCS40/XL Pad Name PQ208 PQ240 BG256 CS280 I/O P90 P105 Y16 GND P91 P106 GND I/O - P107 V15 I/O P92 P108 W16 I/O P93 P109 Y17 I/O P94 P110 V16 I/O P95 P111 ...
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Spartan and Spartan-XL FPGA Families Data Sheet XCS40 and XCS40XL Device Pinouts XCS40/XL Pad Name PQ208 PQ240 BG256 CS280 O, TDO P157 P181 A19 GND P158 P182 GND I/O P159 P183 B18 I/O, P160 P184 B17 (1) PGCK4 , (2) ...
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... I = Industrial T = –40°C to +100° PC84, CS144, and CS280 packages, and VQ100 and BG256 packages for XCS30 only, discontinued by 4. Some Spartan-XL devices are available in Pb-free package options. The Pb-free packages insert a "G" in the package code. Contact Xilinx for availability. Package Specifications ...
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... Notes: 1. PC84, CS144, and CS280 packages, and VQ100 and BG256 packages for XCS30 only, discontinued by 2. These Spartan-XL devices are available in Pb-free package options. The Pb-free packages insert a "G" in the package code. Contact Xilinx for availability. Ordering Information Example: ...
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... Clarified Express Mode pseudo daisy chain. Added new Industrial options. Clarified XCS30XL CS280 V 06/26/08 1.8 Noted that PC84, CS144, and CS280 packages, and VQ100 and BG256 packages for XCS30 only, are discontinued by maximum delay of reconfiguration in page Specifications, page DS060 (v1.8) June 26, 2008 ...