XC5VLX30T-1FFG665CES Xilinx Inc, XC5VLX30T-1FFG665CES Datasheet - Page 382
![IC FPGA VIRTEX-5 ES 30K 665FCBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX30T-1FFG665CES
Manufacturer Part Number
XC5VLX30T-1FFG665CES
Description
IC FPGA VIRTEX-5 ES 30K 665FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX30T-1FFG665CES
Number Of Logic Elements/cells
30720
Number Of Labs/clbs
2400
Total Ram Bits
1327104
Number Of I /o
360
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
665-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Part Number:
XC5VLX30T-1FFG665CES
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Chapter 8: Advanced SelectIO Logic Resources
382
OSERDES VHDL and Verilog Instantiation Templates
Clock Event 2
The reset pulse is deasserted on the rising edge of CLKDIV. The difference in propagation
delay between the two OSERDES causes the SR input to come out of reset on two different
CLK cycles. Without internal retiming, OSERDES1 finishes reset one CLK cycle before
OSERDES0 and both OSERDES are asynchronous.
Clock Event 3
The release of the reset signal at the SR input is retimed internally to CLKDIV. This
synchronizes OSERDES0 and OSERDES1.
Clock Event 4
The release of the reset signal at the SR input is retimed internally to CLK.
The Libraries Guide includes instantiation templates of the OSERDES module in VHDL
and Verilog.
www.xilinx.com
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
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