AT94K40AL-25DQU Atmel, AT94K40AL-25DQU Datasheet - Page 93

• Manufacturer Part Number: AT94K40AL-25DQU
• Description: IC FPSLIC 40K GATE 25MHZ 208PQFP
• Manufacturer: Atmel
• Series: FPSLIC®r

Specifications of AT94K40AL-25DQU

• Core Type: 8-bit AVR
• Speed: 18MHz
• Interface: I²C, UART
• Program Sram Bytes: 20K-32K
• Fpga Sram: 18kb
• Data Sram Bytes: 4K ~ 16K
• Fpga Core Cells: 2304
• Fpga Gates: 40K
• Fpga Registers: 2862
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-MQFP, 208-PQFP
• For Use With: ATSTK594 - BOARD FPSLIC DAUGHTER FOR STK500
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

1138I–FPSLI–1/08
• Bit 6 - PWM0/PWM2: Pulse Width Modulator Enable
When set (one) this bit enables PWM mode for Timer/Counter0 or Timer/Counter2. This mode is
described on
• Bits 5,4 - COM01, COM00/COM21, COM20: Compare Output Mode, Bits 1 and 0
The COMn1 and COMn0 control bits determine any output pin action following a compare match
in Timer/Counter0 or Timer/Counter2. Output pin actions affect pins PE1(OC0) or PE3(OC2).
This is an alternative function to an I/O port, and the corresponding direction control bit must be
set (one) to control an output pin. The control configuration is shown in
Table 1. Compare Output Mode Select
Notes:
• Bit 3 - CTC0/CTC2: Clear Timer/Counter on Compare Match
When the CTC0 or CTC2 control bit is set (one), Timer/Counter0 or Timer/Counter2 is reset to
$00 in the CPU clock-cycle after a compare match. If the control bit is cleared, Timer/Counter
continues counting and is unaffected by a compare match. When a prescaling of 1 is used, and
the compare register is set to C, the timer will count as follows if CTC0/CTC2 is set:
... | C-1 | C | 0 | 1 | ...
When the prescaler is set to divide by 8, the timer will count like this:
... | C-1, C-1, C-1, C-1, C-1, C-1, C-1, C-1 | C, C, C, C, C, C, C, C | 0, 0, 0, 0, 0, 0, 0, 0 | 1, 1, 1, ...
In PWM mode, this bit has a different function. If the CTC0 or CTC2 bit is cleared in PWM mode,
the Timer/Counter acts as an up/down counter. If the CTC0 or CTC2 bit is set (one), the
Timer/Counter wraps when it reaches $FF. Refer to
• Bits 2,1,0 - CS02, CS01, CS00/ CS22, CS21, CS20: Clock Select Bits 2,1 and 0
The Clock Select bits 2,1 and 0 define the prescaling source of Timer/Counter0 and
Timer/Counter2, see
COMn1
1. In PWM mode, these bits have a different function. Refer to
2. n = 0 or 2
0
0
1
1
description.
page
95.
Table 4-13
COMn0
0
1
0
1
and
Table
Description
Timer/Counter disconnected from output pin OCn
Toggles the OCn
Clears the OCn
Sets the OCn
(1)
4-14.
AT94KAL Series FPSLIC
(2)
page 95
(2)
output line (to one).
(2)
output line (to zero).
output line.
for a detailed description.
Table 4-15
Table
for a detailed
1.
(2)
93