CY7C68013A-56BAXC Cypress Semiconductor Corp, CY7C68013A-56BAXC Datasheet - Page 46
![IC MCU USB PERIPH HI SPD 56VFBGA](/photos/6/76/67628/cy7c68013a-56baxc_sml.jpg)
CY7C68013A-56BAXC
Manufacturer Part Number
CY7C68013A-56BAXC
Description
IC MCU USB PERIPH HI SPD 56VFBGA
Manufacturer
Cypress Semiconductor Corp
Series
EZ-USB FX2LP™r
Specifications of CY7C68013A-56BAXC
Program Memory Type
ROMless
Package / Case
56-VFBGA
Applications
USB Microcontroller
Core Processor
8051
Controller Series
CY7C680xx
Ram Size
16K x 8
Interface
I²C, USB, USART
Number Of I /o
24
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Processor Series
CY7C68xx
Core
8051
Data Bus Width
8 bit
Data Ram Size
16 KB
Interface Type
I2C, USART, USB
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
24
Number Of Timers
3
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
CY3684
Minimum Operating Temperature
0 C
Controller Family/series
(8051) USB
Core Size
8 Bit
No. Of I/o's
24
Program Memory Size
16KB
Cpu Speed
48MHz
No. Of Timers
3
Embedded Interface Type
I2C, USART, USB
Rohs Compliant
Yes
Package
56FBGA
Device Core
8051
Family Name
FX2LP
Maximum Speed
48 MHz
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
For Use With
CY4611B - KIT USB TO ATA REFERENCE DESIGN428-1677 - KIT DEVELOPMENT EZ-USB FX2LP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
428-2264
CY7C68013A-56BAXC
Q2748398
CY7C68013A-56BAXC
Q2748398
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY7C68013A-56BAXC
Manufacturer:
ON
Quantity:
2 900
Company:
Part Number:
CY7C68013A-56BAXC
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Part Number:
CY7C68013A-56BAXC
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
Company:
Part Number:
CY7C68013A-56BAXCT
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
10.10 Slave FIFO Asynchronous Write
Table 25. Slave FIFO Asynchronous Write Parameters with Internally Sourced IFCLK
10.11 Slave FIFO Synchronous Packet End Strobe
Table 26. Slave FIFO Synchronous Packet End Strobe Parameters with Internally Sourced IFCLK
Table 27. Slave FIFO Synchronous Packet End Strobe Parameters with Externally Sourced IFCLK
Document #: 38-08032 Rev. *M
t
t
t
t
t
t
t
t
t
t
t
t
t
WRpwl
WRpwh
SFD
FDH
XFD
IFCLK
SPE
PEH
XFLG
IFCLK
SPE
PEH
XFLG
Parameter
Parameter
Parameter
SLWR Pulse LOW
SLWR Pulse HIGH
SLWR to FIFO DATA Setup Time
FIFO DATA to SLWR Hold Time
SLWR to FLAGS Output Propagation Delay
IFCLK Period
PKTEND to Clock Setup Time
Clock to PKTEND Hold Time
Clock to FLAGS Output Propagation Delay
IFCLK Period
PKTEND to Clock Setup Time
Clock to PKTEND Hold Time
Clock to FLAGS Output Propagation Delay
Figure 22. Slave FIFO Synchronous Packet End Strobe Timing Diagram
SLWR/SLCS#
Figure 21. Slave FIFO Asynchronous Write Timing Diagram
PKTEND
FLAGS
DATA
FLAGS
SLWR
IFCLK
Description
Description
Description
t
WRpwl
t
SFD
t
XFD
t
FDH
t
SPE
t
WRpwh
t
t
PEH
XFLG
20.83
20.83
14.6
Min
Min
Min
8.6
2.5
50
70
10
10
0
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
[23]
[20]
Max
Max
Max
13.5
200
9.5
70
[20]
[21]
[21]
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Unit
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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