XE8801AMI000WP Semtech, XE8801AMI000WP Datasheet - Page 25
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XE8801AMI000WP
Manufacturer Part Number
XE8801AMI000WP
Description
SENSING MACHINE WITH 16 + 10 BIT
Manufacturer
Semtech
Datasheet
1.XE8801AMI027LF.pdf
(135 pages)
Specifications of XE8801AMI000WP
Applications
Sensing Machine
Core Processor
RISC
Program Memory Type
FLASH (22 kB)
Controller Series
XE8000
Ram Size
512 x 8
Interface
UART, USRT
Number Of I /o
24
Voltage - Supply
2.4 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
Die
For Use With
XE8000MP - PROG BOARD AND PROSTART2 CARD
Other names
Q2722595
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4.1 Memory organisation
The XE8801AM-SX8801R CPUs are built with Harvard architecture. Harvard architecture uses separate instruction
and data memories. The instruction bus and data bus are also separated. The advantage of such a structure is that
the CPU can get a new instruction and read/write data simultaneously. The circuit configuration is shown in Figure
4-1. The CPU has its 16 internal registers. The instruction memory has a capacity of 8192 22-bit instructions. The
data memory space has 8 low power registers, the peripheral register space and 512 bytes of RAM.
µF µF
Figure 4-1. Memory mapping
The CPU internal registers are described in the CPU chapter. A short reference of the low power registers and
peripheral registers is given in 4.2.
4.2 Quick reference data memory register map
The data register map is given in the tables below. A more detailed description of the different registers is given in
the detailed description of the different peripherals.
The tables give the following information:
The reset source coding is given in Table 4-4-2. To get a full description of the reset sources, please refer to the
reset block chapter.
© Semtech 2005
0h1FFF
0h0000
Instruction
1.
2.
3.
4.
8k x 22bit
capacity:
memory
The register name and register address
The different bits in the register
The access mode of the different bits (see Table 4-4-1 for code description)
The reset source and reset value of the different bits
stat
i0h
i1h
i2h
i3h
iph
r0
r1
r2
r3
a
CPU
i0l
i1l
i2l
i3l
ipl
4-2
0h027F
0h0080
0h007F
0h0008
0h0000
Low power
Peripheral
512 bytes
capacity:
registers
XE8801A – SX8801R
RAM
RAM
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