PIC16F54-I/SS Microchip Technology, PIC16F54-I/SS Datasheet - Page 33

• Manufacturer Part Number: PIC16F54-I/SS
• Description: IC MCU FLASH 512X12 20SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F54-I/SS

• Core Size: 8-Bit
• Program Memory Size: 768B (512 x 12)
• Core Processor: PIC
• Speed: 20MHz
• Peripherals: POR, WDT
• Number Of I /o: 12
• Program Memory Type: FLASH
• Ram Size: 25 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SSOP
• Controller Family/series: PIC16F
• No. Of I/o's: 12
• Ram Memory Size: 25Byte
• Cpu Speed: 20MHz
• No. Of Timers: 1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164307 - MODULE SKT FOR PM3 28SSOPAC164014 - MODULE SKT PROMATEII 44PQFP
• Eeprom Size: -
• Data Converters: -
• Connectivity: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

7.0
The Timer0 module has the following features:
• 8-bit Timer/Counter register, TMR0
• 8-bit software programmable prescaler
• Internal or external clock select
Figure 7-1 is a simplified block diagram of the Timer0
module.
Timer mode is selected by clearing the T0CS bit
(Option<5>). In Timer mode, the Timer0 module will
increment every instruction cycle (without prescaler). If
TMR0 register is written, the increment is inhibited for
the following two cycles (Figure 7-2 and Figure 7-3).
The user can work around this by writing an adjusted
value to the TMR0 register.
FIGURE 7-1:
FIGURE 7-2:
 2004 Microchip Technology Inc.
- Readable and writable
- Edge select for external clock
Note 1:
Instruction
Timer0
PC
(Program
Counter)
Fetch
Instruction
Executed
2:
TIMER0 MODULE AND TMR0
REGISTER
T0CKI
pin
Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in Section 3.4 “Option Register”.
The prescaler is shared with the Watchdog Timer (Figure 7-5).
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
T0
T0SE
PC – 1
TIMER0 BLOCK DIAGRAM
TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALER
F
(1)
OSC
MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
/4
T0 + 1
PC
T0CS
0
1
T0 + 2
Write TMR0
executed
(1)
PC + 1
PS2, PS1, PS0
Programmable
Prescaler
Preliminary
NT0
Read TMR0
reads NT0
3
PC + 2
(2)
(1)
Counter mode is selected by setting the T0CS bit
(Option<5>). In this mode, Timer0 will increment either
on every rising or falling edge of pin T0CKI. The incre-
menting edge is determined by the source edge select
bit T0SE (Option<4>). Clearing the T0SE bit selects the
rising edge. Restrictions on the external clock input are
discussed in detail in Section 7.1 “Using Timer0 with
an External Clock”.
The prescaler assignment is controlled in software by
the control bit PSA (Option<3>). Clearing the PSA bit
will assign the prescaler to Timer0. The prescaler is not
readable or writable. When the prescaler is assigned to
the Timer0 module, prescale values of 1:2, 1:4,...,
1:256 are selectable. Section 7.2 “Prescaler” details
the operation of the prescaler.
A summary of registers associated with the Timer0
module is found in Table 7-1.
PSA
Note:
Read TMR0
reads NT0
NT0
1
0
(1)
PC + 3
PSout
The prescaler may be used by either the
Timer0 module or the Watchdog Timer, but
not both.
(2 cycle delay)
Sync with
Read TMR0
reads NT0
Internal
NT0
Clocks
PC + 4
PSout
Sync
Read TMR0
reads NT0 + 1
NT0 + 1
PIC16F5X
PC + 5
TMR0 reg
Data Bus
DS41213B-page 31
Read TMR0
reads NT0 + 2
NT0 + 2
8
PC + 6