PIC16F54-I/P Microchip Technology, PIC16F54-I/P Datasheet - Page 3

• Manufacturer Part Number: PIC16F54-I/P
• Description: IC MCU FLASH 512X12 18DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F54-I/P

• Program Memory Type: FLASH
• Program Memory Size: 768B (512 x 12)
• Package / Case: 18-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: POR, WDT
• Number Of I /o: 12
• Ram Size: 25 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 25 B
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 1
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: DV164120, DV164101, ICE2000
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DVA16XP180 - ADAPTER DEVICE FOR MPLAB-ICEAC164001 - MODULE SKT PROMATEII 18/28DIP
• Eeprom Size: -
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

FIGURE 2-2:
2.4.2
The ICSPCLK pin is used for clock input and the
ICSPDAT pin is used for data input/output during serial
operation. To input a command, the clock pin is cycled
six times. Each command bit is latched on the falling
edge of the clock with the LSb of the command being
input first. The data must adhere to the setup (T
and hold (T
of the clock (see Table 5-1).
TABLE 2-1:
2.4.2.1
After receiving this command, the chip will load in a
14-bit “data word” when 16 cycles are applied, as
described previously. Because this is a 12-bit core, the
two MSb’s of the data word are ignored. A timing
diagram for the Load Data command is shown in
Figure 2-3.
© 2007 Microchip Technology Inc.
Load Data for Program Memory
Read Data from Program Memory
Increment Address
Begin Programming
End Programming
Bulk Erase Program Memory
ICSPCLK
ICSPDAT
V
V
DD
PP
HLD
SERIAL PROGRAM/VERIFY
OPERATION
Load Data For Program Memory
1) times with respect to the falling edge
Command
COMMAND MAPPING FOR PIC16F54
T
PPDP
ENTERING HIGH
VOLTAGE PROGRAM/
VERIFY MODE
T
HLD
0
x
x
x
x
x
x
SET
Preliminary
1)
x
x
x
x
x
x
Mapping (MSb … LSb)
0
0
0
1
1
1
Commands that do not have data associated with them
are required to wait a minimum of T
from the falling edge of the last command clock to the
rising edge of the next command clock (see Table 5-1).
Commands that do have data associated with them
(Read and Load), are also required to wait T
between the command and the data segment. This is
measured from the falling edge of the last command
clock to the rising edge of the first data clock. The data
segment, consisting of 16 clock cycles, can begin after
this delay.
The first and last clock pulses during the data segment
correspond to the Start and Stop bits, respectively.
Input data is a “don't care” during the Start and Stop
cycles. The 14 clock pulses between the Start and Stop
cycles clock the 14 bits of input/output data. Data is
transferred LSb first.
During Read commands, in which the data is output
from the PIC16FXXXX, the ICSPDAT pin transitions
from the high-impedance state to the low-impedance
output state at the rising edge of the second data clock
(first clock edge after the Start cycle). The ICSPDAT pin
returns to the high-impedance state at the rising edge
of the 16th data clock (first edge of the Stop cycle). See
Figure 2-4.
The commands that are available are described in
Table 2-1.
Note:
0
1
1
0
1
0
After every End Programming command,
a delay of T
1
0
1
0
1
0
0
0
0
0
0
1
DIS
is required.
0, data (14), 0
0, data (14), 0
Externally Timed
Internally Timed
PIC16F54
DS41207D-page 3
Data
DLY
2 measured
DLY
2