Z8018006PSG Zilog, Z8018006PSG Datasheet - Page 6
![IC 6MHZ Z180 CMOS ENH MPU 64-DIP](/photos/6/76/67660/z8018006psg_sml.jpg)
Z8018006PSG
Manufacturer Part Number
Z8018006PSG
Description
IC 6MHZ Z180 CMOS ENH MPU 64-DIP
Manufacturer
Zilog
Datasheet
1.Z8018006PSG.pdf
(85 pages)
Specifications of Z8018006PSG
Processor Type
Z180
Features
8-Bit, Enhanced Z80 Megacell
Speed
6MHz
Voltage
5V
Mounting Type
Through Hole
Package / Case
64-DIP (0.750", 19.05mm)
Processor Series
Z8018xx
Core
Z80
Data Bus Width
8 bit
Maximum Clock Frequency
6 MHz
Number Of Timers
2
Operating Supply Voltage
0 V to 5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
Through Hole
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3881
Q2456016
Z8018006PSG
Q2456016
Z8018006PSG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z8018006PSG
Manufacturer:
Zilog
Quantity:
104
Company:
Part Number:
Z8018006PSG
Manufacturer:
Zilog
Quantity:
151
PS014004-1106
DMA Source Address Register Channel 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
DMA Destination Address Register Channel 0 . . . . . . . . . . . . . . . . . . . . . . . . . 55
DMA Byte Count Register Channel 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
DMA Memory Address Register Channel 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
DMA I/O Address Register Channel 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
DMA/WAIT Control Register (DCNTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Interrupt Vector Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Int/TRAP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Refresh Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
MMU Common Base Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
MMU Bank Base Register (BBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
MMU Common/Bank Area Register (CBAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Operation Mode Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
I/O Control Register (ICR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Customer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
DMA Source Address Register, Channel 0L . . . . . . . . . . . . . . . . . . . . . . . . 54
DMA Source Address Register, Channel 0H . . . . . . . . . . . . . . . . . . . . . . . 55
DMA Source Address Register Channel 0B . . . . . . . . . . . . . . . . . . . . . . . . 55
DMA Destination Address Register Channel 0L . . . . . . . . . . . . . . . . . . . . . 56
DMA Destination Address Register Channel 0H . . . . . . . . . . . . . . . . . . . . . 56
DMA Destination Address Register Channel 0B . . . . . . . . . . . . . . . . . . . . . 56
DMA Byte Count Register Channel 0L . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
DMA Byte Count Register Channel 0H . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
DMA Byte Count Register Channel 1L . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
DMA Byte Count Register Channel 1H . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
DMA Memory Address Register, Channel 1L . . . . . . . . . . . . . . . . . . . . . . . 59
DMA Memory Address Register, Channel 1H . . . . . . . . . . . . . . . . . . . . . . . 60
DMA Memory Address Register, Channel 1B . . . . . . . . . . . . . . . . . . . . . . . 60
DMA I/O Address Register Channel 1L . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
DMA I/O Address Register Channel 1H . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
DMA I/O Address Register Channel 1B . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
DMA Status Register (DSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
DMA Mode Register (DMODE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Microprocessor Unit
vi