Z8018008PSG Zilog, Z8018008PSG Datasheet - Page 29
![IC 8MHZ Z180 CMOS ENH MPU 64-DIP](/photos/6/76/67662/z8018008psg_sml.jpg)
Z8018008PSG
Manufacturer Part Number
Z8018008PSG
Description
IC 8MHZ Z180 CMOS ENH MPU 64-DIP
Manufacturer
Zilog
Datasheet
1.Z8018006PSG.pdf
(85 pages)
Specifications of Z8018008PSG
Processor Type
Z180
Features
8-Bit, Enhanced Z80 Megacell
Speed
8MHz
Voltage
5V
Mounting Type
Through Hole
Package / Case
64-DIP (0.750", 19.05mm)
Processor Series
Z8018xx
Core
Z80
Data Bus Width
8 bit
Maximum Clock Frequency
8 MHz
Number Of Timers
2
Operating Supply Voltage
0 V to 5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
Through Hole
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3884
Z8018008PSG
Z8018008PSG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z8018008PSG
Manufacturer:
ZILOG
Quantity:
5 530
Company:
Part Number:
Z8018008PSG
Manufacturer:
ZILOG
Quantity:
6 250
Company:
Part Number:
Z8018008PSG
Manufacturer:
Zilog
Quantity:
153
Table 7. Z80180-6 AC Characteristics (continued)
PS014004-1106
No
20
21
22
23
24
25
26
26a
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
P
P
t
t
Symbol Item
WH
WDZ
WRD1
WDD
WDS
WRD2
WRP
WDH
IOD1
IOD2
IOD3
INTS
INTS
NMIW
BRS
BRH
BAD1
BAD2
BZD
MEWH
MEWL
RFD1
RFD2
HAD1
HAD2
DRQS
DRQH
TED1
TED2
ED1
ED2
Er
Ef
WEH
WEL
WAIT Hold Time from Ø Fall
Ø Rise to Data Float Delay
Ø Rise to WR Fall Delay
Ø Fall to WRITE Data Delay Time
WRITE Data Set-up Time to WR Fall
Ø Fall to WR Rise Delay
WR Pulse Width
WR Pulse Width (I/O WRITE Cycle)
WRITE Data Hold Time from (WR Rise
Ø Fall to IORQ Fall Delay
Ø Rise to IORQ Fall Delay
Ø Fall to IORQ Rise Delay
M1 Fall to IORQ Fall Delay
INT Set-up Time to Ø Fall
INT Hold Time from Ø Fall
NMI Pulse Width
BUSREQ Set-up Time to Ø Fall
BUSREQ Hold Time from Ø Fall
Ø Rise to BUSACK Fall Delay
Ø Fall to BUSACK Rise Delay
Ø Rise to Bus Floating Delay Time
MREQ Pulse Width (High)
MREQ Pulse Width (Low)
Ø Rise to RFSH Fall Delay
Ø Rise to RFSH Rise Delay
Ø Rise to HALT Fall Delay
Ø Rise to HALT Rise Delay
/DREQi Set-up Time to Ø Rise
/DREQi Hold Time from Ø Rise
Ø Fall to TENDi Fall Delay
Ø Fall to TENDi Rise Delay
Ø Rise to E Rise Delay
Ø Fall or Rise to E Fall Delay
E Pulse Width (High)
E Pulse Width (Low)
Enable Rise Time
Enable Fall Time
IOC = 1
IOC = 1
)
Z80180-6
Min
40
–
–
40
–
170
40
–
40
40
40
–
–
–
–
–
–
–
–
–
–
–
332
–
–
340
40
120
110
125
40
40
–
75
180
–
–
Max
–
95
65
90
–
80
–
–
–
60
65
60
–
–
–
–
–
–
95
90
125
–
–
90
90
90
90
–
–
70
70
95
95
–
–
20
20
Microprocessor Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Architecture
Z80180
23