Z8S18010FSG Zilog, Z8S18010FSG Datasheet - Page 24
![IC 10MHZ STATIC Z180 80-QFP](/photos/6/76/67663/269-80-qfp_sml.jpg)
Z8S18010FSG
Manufacturer Part Number
Z8S18010FSG
Description
IC 10MHZ STATIC Z180 80-QFP
Manufacturer
Zilog
Datasheet
1.Z8S18010PSG.pdf
(71 pages)
Specifications of Z8S18010FSG
Processor Type
Z180
Features
Enhanced Z180
Speed
10MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
80-BQFP
Processor Series
Z8S180X
Core
Z80
Data Bus Width
8 bit
Maximum Clock Frequency
10 MHz
Number Of Timers
2
Operating Supply Voltage
0 V to 3.3 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
Z8S18000ZEM
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-4296
Z8S18010FSG
Z8S18010FSG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z8S18010FSG
Manufacturer:
Zilog
Quantity:
426
is
Figure 18 indicates the timing of this sequence. The device
takes 64 or 2
ing the bus to an external Master during
when the
As described previously for
the MPU leaves
abled
IE instruction, it starts by performing the interrupt with the
return address being that of the instruction following the
mode due to an external interrupt request that's enabled in
the
While the Z8S180/Z8L180 is in
the bus to an external Master if the
1
.
instruction. If the Z8S180/Z8L180 leaves
–
17
Control Register, but the
(131,072) clock cycles to grant the bus de-
bit in the CPU Control Register (
Low when the
mode due to
and
, flag is
bit (
, bit is
mode, it grants
Low or an en-
modes, when
1
due to an
0
mode,
due to
) is
1
)
.
a
struction(s) following the
or
tion delay, the Z8S180/Z8L180 stays in
Figure 17 indicates the timing for leaving
due to an interrupt request.
pending on the CCR3 bit. The latter (not the
external Masters. If so,
can be used.
instruction, the processor restarts by executing the in-
The Z8S180/Z8L180 takes either 64 or 2
clocks to restart, depending on the CCR3 bit.
goes inactive before the end of the clock stabiliza-
) case may be prohibitive for many demand-driven
instruction. If
or
17
(131,072)
, or
ZiLOG
mode.
mode
mode