MPC855TCVR50D4 Freescale Semiconductor, MPC855TCVR50D4 Datasheet - Page 3
![IC MPU POWERQUICC 50MHZ 357PBGA](/photos/6/76/67680/mfg_mpc860_series_sml.jpg)
MPC855TCVR50D4
Manufacturer Part Number
MPC855TCVR50D4
Description
IC MPU POWERQUICC 50MHZ 357PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MPC855TVR50D4.pdf
(15 pages)
2.MPC8555ECVTALF.pdf
(88 pages)
3.MPC855TCVR50D4.pdf
(80 pages)
Specifications of MPC855TCVR50D4
Processor Type
MPC8xx PowerQUICC 32-Bit
Speed
50MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
357-PBGA
Processor Series
MPC8xx
Core
MPC8xx
Data Bus Width
32 bit
Maximum Clock Frequency
50 MHz
Operating Supply Voltage
2.5 V, 3.3 V
Maximum Operating Temperature
+ 95 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Family Name
MPC8xx
Device Core
PowerQUICC
Device Core Size
32b
Frequency (max)
50MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
2.5/3.3V
Operating Supply Voltage (max)
3.465/3.6V
Operating Supply Voltage (min)
2/3.135V
Operating Temp Range
-40C to 95C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
357
Package Type
BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC855TCVR50D4
Manufacturer:
FREESCAL
Quantity:
246
Company:
Part Number:
MPC855TCVR50D4
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC855TCVR50D4R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Freescale Semiconductor
•
•
Security Engine is optimized to handle all the algorithms associated with IPSec, SSL/TLS, SRTP,
IEEE Std 802.11i™, iSCSI, and IKE processing. The Security Engine contains 4 Crypto-channels,
a Controller, and a set of crypto Execution Units (EUs). The Execution Units are:
— Public Key Execution Unit (PKEU) supporting the following:
— Data Encryption Standard Execution Unit (DEU)
— Advanced Encryption Standard Unit (AESU)
— ARC Four execution unit (AFEU)
— Message Digest Execution Unit (MDEU)
— Random Number Generator (RNG)
— 4 Crypto-channels, each supporting multi-command descriptor chains
High-performance RISC CPM operating at up to 333 MHz
— CPM software compatibility with previous PowerQUICC families
— One instruction per clock
— Executes code from internal ROM or instruction RAM
— 32-bit RISC architecture
— Tuned for communication environments: instruction set supports CRC computation and bit
— Internal timer
— Interfaces with the embedded e500 core processor through a 32-Kbyte dual-port RAM and
— Handles serial protocols and virtual DMA
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
– RSA and Diffie-Hellman
– Programmable field size up to 2048-bits
– Elliptic curve cryptography
– F2m and F(p) modes
– Programmable field size up to 511-bits
– DES, 3DES
– Two key (K1, K2) or Three Key (K1, K2, K3)
– ECB and CBC modes for both DES and 3DES
– Implements the Rinjdael symmetric key cipher
– Key lengths of 128, 192, and 256 bits.Two key
– ECB, CBC, CCM, and Counter modes
– Implements a stream cipher compatible with the RC4 algorithm
– 40- to 128-bit programmable key
– SHA with 160-bit or 256-bit message digest
– MD5 with 128-bit message digest
– HMAC with either algorithm
– Static and/or dynamic assignment of crypto-execution units via an integrated controller
– Buffer size of 256 Bytes for each execution unit, with flow control for large data sizes
manipulation.
virtual DMA channels for each peripheral controller
Overview
3