MPC8541EVTAPF Freescale Semiconductor, MPC8541EVTAPF Datasheet - Page 10

IC MPU POWERQUICC III 783-FCPBGA

MPC8541EVTAPF

Manufacturer Part Number
MPC8541EVTAPF
Description
IC MPU POWERQUICC III 783-FCPBGA
Manufacturer
Freescale Semiconductor
Series
PowerQUICC IIIr
Datasheets

Specifications of MPC8541EVTAPF

Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
833MHz
Voltage
1.2V
Mounting Type
Surface Mount
Package / Case
783-FCPBGA
Core Size
32 Bit
Program Memory Size
64KB
Cpu Speed
833MHz
Digital Ic Case Style
BGA
No. Of Pins
783
Supply Voltage Range
1.14V To 1.26V
Rohs Compliant
Yes
Family Name
MPC85XX
Device Core
PowerQUICC III
Device Core Size
32b
Frequency (max)
833MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
1.2V
Operating Supply Voltage (max)
1.26V
Operating Supply Voltage (min)
1.14V
Operating Temp Range
0C to 105C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
783
Package Type
FCBGA
For Use With
MPC8548CDS - DEV TOOLS CDS FOR 8548CWH-PPC-8540N-VE - KIT EVAL SYSTEM MPC8540
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant

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Electrical Characteristics
Figure 2
The MPC8541E core voltage must always be provided at nominal 1.2 V (see
recommended core voltage). Voltage to the processor interface I/Os are provided through separate sets of
supply pins and must be provided at the voltages shown in
respect to the associated I/O supply voltage. OV
circuits and satisfy appropriate LVCMOS type specifications. The DDR SDRAM interface uses a
single-ended differential receiver referenced the externally supplied MV
GV
10
DD
/2) as is appropriate for the SSTL2 electrical signaling standard.
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
shows the undershoot and overshoot voltages at the interfaces of the MPC8541E.
V
V
Note:
IH
1. Note that t
IL
Figure 2. Overshoot/Undershoot Voltage for GV
G/L/OV
G/L/OV
GND – 0.3 V
GND – 0.7 V
G/L/OV
DD
DD
SYS
+ 20%
+ 5%
GND
refers to the clock period associated with the SYSCLK signal.
DD
DD
and LV
Not to Exceed 10%
Table
of t
DD
SYS
based receivers are simple CMOS I/O
2. The input voltage threshold scales with
1
DD
/OV
REF
DD
signal (nominally set to
/LV
Table 2
DD
Freescale Semiconductor
for actual

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