MPC857DSLVR50B Freescale Semiconductor, MPC857DSLVR50B Datasheet - Page 2

• Manufacturer Part Number: MPC857DSLVR50B
• Description: IC MPU POWERQUICC 50MHZ 357-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC857DSLVR50B

• Processor Type: MPC8xx PowerQUICC 32-Bit
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Processor Series: MPC85xx
• Core: MPC8xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Operating Supply Voltage: 2.5 V, 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Family Name: MPC8xx
• Device Core: PowerQUICC
• Device Core Size: 32b
• Frequency (max): 50MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.465/3.6V
• Operating Supply Voltage (min): 2/3.135V
• Operating Temp Range: 0C to 105C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 357
• Package Type: BGA
• Leaded Process Compatible: Yes
• Rohs Compliant: Yes
• Peak Reflow Compatible (260 C): Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Overview
1
The MPC862/857T/857DSL is a derivative of Freescale’s MPC860 PowerQUICC™ family of devices. It
is a versatile single-chip integrated microprocessor and peripheral combination that can be used in a
variety of controller applications and communications and networking systems. The
MPC862/857T/857DSL provides enhanced ATM functionality over that of other ATM-enabled members
of the MPC860 family.
Table 1
2
The following list summarizes the key MPC862/857T/857DSL features:
2
•
Overview
Features
Embedded single-issue, 32-bit MPC8xx core (implementing the PowerPC architecture) with
thirty-two 32-bit general-purpose registers (GPRs)
— The core performs branch prediction with conditional prefetch, without conditional execution
— 4- or 8-Kbyte data cache and 4- or 16-Kbyte instruction cache (see
— MMUs with 32-entry TLB, fully associative instruction and data TLBs
— MMUs support multiple page sizes of 4, 16, and 512 Kbytes, and 8 Mbytes; 16 virtual address
— Advanced on-chip-emulation debug mode
shows the functionality supported by the members of the MPC862/857T/857DSL family.
– 16-Kbyte instruction cache (MPC862P) is four-way, set-associative with 256 sets; 4-Kbyte
– 8-Kbyte data cache (MPC862P) is two-way, set-associative with 256 sets; 4-Kbyte data
– Cache coherency for both instruction and data caches is maintained on 128-bit (4-word)
– Caches are physically addressed, implement a least recently used (LRU) replacement
spaces and 16 protection groups
instruction cache (MPC862T, MPC857T, and MPC857DSL) is two-way, set-associative
with 128 sets.
cache (MPC862T, MPC857T, and MPC857DSL) is two-way, set-associative with 128 sets.
cache blocks.
algorithm, and are lockable on a cache block basis.
1
2
MPC862P
MPC862T
MPC857T
MPC857DSL
not support the Time Slot Assigner (TSA).
On the MPC857DSL, the SCC (SCC1) is for ethernet only. Also, the MPC857DSL does
On the MPC857DSL, the SMC (SMC1) is for UART only.
MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev. 3
Part
Instruction
16 Kbyte
4 Kbyte
4 Kbyte
4 Kbyte
Cache
Table 1. MPC862 Family Functionality
Cache
Data Cache
8 Kbyte
4 Kbyte
4 Kbyte
4 Kbyte
Up to 4
Up to 4
10T
1
1
Ethernet
10/100
1
1
1
1
SCC
Table
1
1
4
4
1
Freescale Semiconductor
SMC
1).
1
2
2
2
2