MPC8315ECVRAGDA Freescale Semiconductor, MPC8315ECVRAGDA Datasheet - Page 67

MPU POWERQUICC II PRO 620-PBGA

MPC8315ECVRAGDA

Manufacturer Part Number
MPC8315ECVRAGDA
Description
MPU POWERQUICC II PRO 620-PBGA
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MPC8315ECVRAGDA

Processor Type
MPC83xx PowerQUICC II Pro 32-Bit
Speed
400MHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
620-PBGA
Processor Series
MPC8xxx
Core
e300
Data Bus Width
32 bit
Maximum Clock Frequency
50 MHz
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Leaded Process Compatible
Yes
Rohs Compliant
Yes
Peak Reflow Compatible (260 C)
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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16.4.3
Table 55
specified at the component pins.
Freescale Semiconductor
Unit interval
Differential peak-to-peak
output voltage
Minimum receiver eye
width
Parameter
defines the specifications for the differential input at all receivers (RXs). The parameters are
Figure 50. Minimum Transmitter Timing and Voltage Output Compliance Specifications
Differential Receiver (RX) Input Specifications
MPC8315E PowerQUICC
Table 55. Differential Receiver (RX) Input Specifications
(D+ D– Crossing Point)
V
Symbol
RX-DIFFp-p
T
RX-EYE
V
TX-DIFF
UI
= 0 mV
566 mV (3 dB) >= V
0.7 UI = UI – 0.3 UI(J
Each UI is 400 ps ± 300 ppm.
UI does not account for
Spread Spectrum Clock
dictated variations.
V
V
The maximum interconnect
media and Transmitter jitter
that can be tolerated by the
Receiver can be derived as
T
U
II Pro Processor Hardware Specifications, Rev. 0
RX-MAX-JITTER
RX-DIFFp-p
RX-D-
RX-EYE
V
V
[De-emphasized Bit]
TX-DIFFp-p-MIN
TX-DIFFp-p-MIN
|
[Transition Bit]
[Transition Bit]
= 0.6 UI.
Comments
TX-DIFFp-p-MIN
= 2*|V
= 800 mV
= 800 mV
= 1 -
TX-TOTAL-MAX
RX-D+
>= 505 mV (4 dB)
-
(D+ D– Crossing Point)
)
V
TX-DIFF
399.88
0.175
Min
0.4
= 0 mV
Typical
400
400.12
1.200
Max
Units
ps
UI
V
PCI Express
Notes
2, 3
1
2
67

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