MPC8248VRTIEA Freescale Semiconductor, MPC8248VRTIEA Datasheet - Page 21

• Manufacturer Part Number: MPC8248VRTIEA
• Description: IC MPU POWERQUICC II 516-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8248VRTIEA

• Processor Type: MPC82xx PowerQUICC II 32-bit
• Speed: 400MHz
• Voltage: 1.5V
• Mounting Type: Surface Mount
• Package / Case: 516-PBGA
• Family Name: MPC82XX
• Device Core: PowerQUICC II
• Device Core Size: 32b
• Frequency (max): 400MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Operating Temp Range: 0C to 105C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 516
• Package Type: TEPBGA
• For Use With: CWH-PPC-8248N-VE - KIT EVAL SYSTEM QUICCSTART 8248
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Table 12
Freescale Semiconductor
1
1
2
3
Spec Number
Spec Number
Setup
sp31
sp32
sp33
sp34
sp35
Max
sp11
sp12
sp13
sp15
measured at the pin.
measured at the pin.
Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings are
Value is for ADD only; other sp32/sp30 signals are not applicable.
To achieve 1 ns of hold time at 66.67/83.33/100 MHZ, a minimum loading of 20 pF is required.
Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN. Timings are
sp30
sp30
sp30
sp30
sp30
Min
Hold
sp10 AACK/TA/TS/DBG/BG/BR/ARTRY/TEA
sp10 Data bus in normal mode
sp10 Data bus in pipeline mode (without ECC and
sp10 All other pins
lists SIU output characteristics.
PARITY)
PSDVAL/TEA/TA
ADD/ADD_atr./BADDR/CI/GBL/WT
Data bus
Memory controller signals/ALE
All other signals
The following conditions must be met in order to operate the MPC8272
family devices with 133 MHz bus: single PowerQUICC II Bus mode must
be used (no external master, BCR[EBM] = 0); data bus must be in Pipeline
mode (BRx[DR] = 1); internal arbiter and memory controller must be used.
For expected load of above 40 pF, it is recommended that data and address
buses be configured to low (25 Ω) impedance (SIUMCR[HLBE0] = 1,
SIUMCR[HLBE1] = 1).
3
MPC8272 PowerQUICC II™ Family Hardware Specifications, Rev. 2
Characteristic
Characteristic
Table 12. AC Characteristics for SIU Outputs
Table 11. AC Characteristics for SIU Inputs
NOTE: Conditions
MHz
6.5
66
MHz
7
8
6
6
N/A
66
6
5
5
Maximum Delay
MHz
6.5
6.5
5.5
5.5
MHz
83
6
83
5
4
4
4
Setup
MHz
100
5.5
5.5
5.5
5.5
5.5
MHz
100
3.5
3.5
2.5
3.5
1
MHz
4.5
133
N/A
N/A
4.5
4.5
MHz
1
Value (ns)
133
N/A
N/A
N/A
Value (ns)
1.5
2
MHz
MHz
0.8
N/A
66
0.5
0.5
0.5
66
1
1
1
1
AC Electrical Characteristics
Minimum Delay
MHz
MHz
0.8
83
0.5
0.5
0.5
0.5
83
1
1
1
1
Hold
MHz
MHz
100
100
0.8
0.5
0.5
0.5
0.5
1
1
1
1
MHz
MHz
133
N/A
N/A
N/A
133
N/A
N/A
0.5
1
1
1
2
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