MPC860ENCZQ50D4 Freescale Semiconductor, MPC860ENCZQ50D4 Datasheet - Page 39
MPC860ENCZQ50D4
Manufacturer Part Number
MPC860ENCZQ50D4
Description
IC MPU POWERQUICC 50MHZ 357PBGA
Manufacturer
Freescale Semiconductor
Series
PowerQUICC Ir
Datasheet
1.MC860DECVR50D4R2.pdf
(80 pages)
Specifications of MPC860ENCZQ50D4
Processor Type
MPC8xx PowerQUICC 32-Bit
Speed
50MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
357-PBGA
Processor Series
MPC8xx
Core
MPC8xx
Data Bus Width
32 bit
Maximum Clock Frequency
50 MHz
Operating Supply Voltage
2.5 V, 3.3 V
Maximum Operating Temperature
+ 95 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Core Size
32 Bit
Program Memory Size
8KB
Cpu Speed
50MHz
Embedded Interface Type
Ethernet, I2C, SPI, UART
Digital Ic Case Style
BGA
No. Of Pins
357
Rohs Compliant
No
Family Name
MPC8xx
Device Core
PowerQUICC
Device Core Size
32b
Frequency (max)
50MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
2.5/3.3V
Operating Supply Voltage (max)
3.465/3.6V
Operating Supply Voltage (min)
2/3.135V
Operating Temp Range
-40C to 95C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
357
Package Type
BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC860ENCZQ50D4
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MPC860ENCZQ50D4
Manufacturer:
FREE
Quantity:
20 000
Table 12
Freescale Semiconductor
Num
R69 CLKOUT to HRESET high impedance
R70 CLKOUT to SRESET high impedance
R71 RSTCONF pulse width
R72 —
R73 Configuration data to HRESET rising edge
R74 Configuration data to RSTCONF rising
R75 Configuration data hold time after
R76 Configuration data hold time after
R77 HRESET and RSTCONF asserted to data
R78 RSTCONF negated to data out high
R79 CLKOUT of last rising edge before chip
R80 DSDI, DSCK setup
R81 DSDI, DSCK hold time
R82 SRESET negated to CLKOUT rising edge
setup time
edge setup time
RSTCONF negation
HRESET negation
out drive
impedance
three-state HRESET to data out high
impedance
for DSDI and DSCK sample
shows the reset timing for the MPC860.
Characteristic
MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8
Table 12. Reset Timing
515.15
504.55
350.00
242.42
90.91
0.00
0.00
0.00
Min
—
—
—
—
—
—
33 MHz
20.00
20.00
25.00
25.00
25.00
Max
—
—
—
—
—
—
—
—
—
425.00
425.00
350.00
200.00
75.00
0.00
0.00
0.00
Min
—
—
—
—
—
40 MHz
20.00
20.00
25.00
25.00
25.00
Max
—
—
—
—
—
—
—
—
340.00
350.00
350.00
160.00
60.00
0.00
0.00
0.00
Min
—
—
—
—
—
—
50 MHz
20.00
20.00
25.00
25.00
25.00
Max
—
—
—
—
—
—
—
—
—
257.58
277.27
350.00
121.21
45.45
0.00
0.00
0.00
Min
—
—
—
—
—
—
66 MHz
Bus Signal Timing
20.00
20.00
25.00
25.00
25.00
Max
—
—
—
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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