Z8S18020VSC00TR Zilog, Z8S18020VSC00TR Datasheet - Page 21

• Manufacturer Part Number: Z8S18020VSC00TR
• Description: IC Z180 MPU 68PLCC
• Manufacturer: Zilog

Specifications of Z8S18020VSC00TR

• Processor Type: Z180
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

lowed by execution of the
cannot generate a recovery interrupt.
ZiLOG
This condition provides a technique for synchronization
with high-speed external events without incurring the la-
tency imposed by an interrupt-response sequence. Figure 14
depicts the timing for exiting
rupt request.
case, on-chip I/O (ASCI, CSI/O, PRT) stops operating.
However, the CPU continues to operate. Recovery from
bination of
mode is entered by setting the
chip I/O and CPU stop operating, reducing power consump-
tion, but the
mode except that internal I/O sources (disabled by
mode by performing the following actions:
The oscillator keeps operating but its output is blocked to
all circuitry including the
Set the
Set
Set
Execute the
to
0
.
mode is performed by resetting the
bit of the I/O Control Register (
Software puts the Z8S180/Z8L180 into this
to
to
output continues to operate. Recovery from
mode is the same as recovery from
and
bit (
instruction
mode is entered by setting the
) to
instruction. In this mode, on-
pin. DRAM refresh and all
modes.
mode due to an inter-
bit in
mode is the com-
) to
to
1
. In this
1
bit in
fol-
)
internal devices stop, but external interrupts can occur. Bus
granting to external Masters can occur if the
the CPU control Register (
mode was entered.
The Z8S180/Z8L180 leaves
Low on
external interrupt request on
abled in the INT/TRAP Control Register. As previously de-
scribed for
terrupt request when the
tion, the device starts by performing the interrupt with the
return address of the instruction after the
If an external interrupt enables the INT/TRAP control reg-
ister while the
mode; specifically, the processor restarts by executing the
instructions following the
Figure 15 indicates the timing for exiting
to an interrupt request.
mode due to an
The Z8S180/Z8L180 takes about 9.5 clocks to restart.
The Z8S180/Z8L180 takes about 1.5 clock ticks to re-
start.
, an external interrupt request on
mode, when the Z8S180/Z8L180 leaves
bit is
, or due to an enabled external in-
0
, Z8S180/Z8L180 leaves
flag is
instruction.
) was set to
,
mode in response to a
1
due to an
or
1
instruction.
before
mode due
that is en-
instruc-
, or an
bit in