EZ80190AZ050EC00TR Zilog, EZ80190AZ050EC00TR Datasheet - Page 147
![IC EZ80 ACCLAIM 50MHZ 100LQFP](/photos/6/76/67664/269-100-lqfp_sml.jpg)
EZ80190AZ050EC00TR
Manufacturer Part Number
EZ80190AZ050EC00TR
Description
IC EZ80 ACCLAIM 50MHZ 100LQFP
Manufacturer
Zilog
Datasheet
1.EZ80190AZ050SG.pdf
(221 pages)
Specifications of EZ80190AZ050EC00TR
Processor Type
eZ80
Features
High Speed, Single-Cycle Instruction-Fetch
Speed
50MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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Interrupt Controller
PS006614-1208
The interrupt controller on the eZ80190 device routes the interrupt request signals from
the internal peripherals and external devices (via the internal port I/O) to the eZ80
On the eZ80190 device, all interrupts use the CPU’s vectored interrupt function.
lists the vector for each of the interrupt sources. The interrupt sources are listed in order of
their priority, with vector
Table 74. Interrupt Vector Sources by Priority
When any one or more of the interrupt requests (IRQs) become active, an interrupt request
is generated by the interrupt controller and sent to the CPU. The corresponding 8-bit inter-
rupt vector for the highest priority interrupt is placed on the 8-bit interrupt vector bus,
IVECT[7:0]. The interrupt vector bus is internal to the eZ80190 device and is therefore
not visible externally. The response time of the CPU to an interrupt request is a function of
the current instruction being executed as well as the number of WAIT states being
inserted. The interrupt vector, {I[7:0], IVECT[7:0]}, is visible on the address bus,
ADDR[16:0], when the Interrupt Service Routine (ISR) begins. The response of the CPU
to a vectored interrupt on the eZ80190 device is listed in
does not support eZ80 Mode 0, Mode 1, or Mode 2 interrupts. Interrupt sources are
required to be active until the ISR starts.
Vector
0Ah
0Ch
0Eh
00h
02h
04h
06h
08h
10h
12h
14h
16h
Port A 0
Source
DMA 0
DMA 1
MACC
PRT 0
PRT 1
PRT 2
PRT 3
PRT 4
PRT 5
UZI 0
UZI 1
Vector
1Ah
1Ch
1Eh
2Ah
2Ch
2Eh
18h
20h
22h
24h
26h
28h
00h
being the highest-priority interrupt.
Port A 1
Port A 2
Port A 3
Port A 4
Port A 5
Port A 6
Port A 7
Port B 0
Port B 1
Port B 2
Port B 3
Port B 4
Source
Vector
3Ah
3Ch
3Eh
30h
32h
34h
36h
38h
40h
42h
44h
46h
Port C 0
Port C 1
Port C 2
Port C 3
Port C 4
Port C 5
Port C 6
Port C 7
Port D 0
Table
Port B 5
Port B 6
Port B 7
Source
75. The eZ80190 device
Product Specification
Vector
4Ch
5Ch
4Ah
4Eh
5Ah
5Eh
48h
50h
52h
54h
56h
58h
Interrupt Controller
Reserved
Reserved
Reserved
Reserved
Reserved
Port D 1
Port D 2
Port D 3
Port D 4
Port D 5
Port D 6
Port D 7
Source
eZ80190
Table 74
®
CPU.
137
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