EZ80L92AZ020SC Zilog, EZ80L92AZ020SC Datasheet - Page 13

• Manufacturer Part Number: EZ80L92AZ020SC
• Description: IC WEBSERVER 20MHZ 100LQFP
• Manufacturer: Zilog

Specifications of EZ80L92AZ020SC

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 20MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3168; EZ80L92AZ020SC

Table 1. 100-Pin LQFP Pin Identification of eZ80L92 MCU (Continued)
PS013014-0107
Pin No
14
15
16
17
18
19
20
ADDR11
ADDR12
ADDR13
ADDR14
ADDR15
Symbol
V
V
DD
SS
Function
Address Bus
Address Bus
Address Bus
Address Bus
Power Supply
Ground
Address Bus
Signal Direction
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Configured as an output in normal
operation. The address bus selects a
location in memory or I/O space to be
read or written. Configured as an input
during bus acknowledge cycles. Drives
the Chip Select/Wait State Generator
block to generate Chip Selects.
Configured as an output in normal
operation. The address bus selects a
location in memory or I/O space to be
read or written. Configured as an input
during bus acknowledge cycles. Drives
the Chip Select/Wait State Generator
block to generate Chip Selects.
Configured as an output in normal
operation. The address bus selects a
location in memory or I/O space to be
read or written. Configured as an input
during bus acknowledge cycles. Drives
the Chip Select/Wait State Generator
block to generate Chip Selects.
Configured as an output in normal
operation. The address bus selects a
location in memory or I/O space to be
read or written. Configured as an input
during bus acknowledge cycles. Drives
the Chip Select/Wait State Generator
block to generate Chip Selects.
Power Supply.
Ground.
Configured as an output in normal
operation. The address bus selects a
location in memory or I/O space to be
read or written. Configured as an input
during bus acknowledge cycles. Drives
the Chip Select/Wait State Generator
block to generate Chip Selects.
Description
Product Specification
Architectural Overview
7