Z84C9010VEC Zilog, Z84C9010VEC Datasheet - Page 11

• Manufacturer Part Number: Z84C9010VEC
• Description: IC 10MHZ Z80 KIO XTEMP 84-PLCC
• Manufacturer: Zilog

Specifications of Z84C9010VEC

• Processor Type: Z80
• Features: Serial/Parallel Input/Output, Counter/Timer Circuit
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 84-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

PS011802-0902
Note:
Note:
ASTB, BSTB. Port Strobe (inputs, Active Low). These signals indicate that the peripheral
device has performed a transfer. In Mode 0, the signal indicates that the peripheral device
has accepted the data present on the port pins. In Mode 1, the signal causes the data on the
port pins to be latched onto Port A. In Mode 2, ASTB Low causes the data in the output
data latch of Port A to be placed onto the Port A pins. BSTB Low causes the data present
on the Port A pins to be latched into the Port A input data latch. The end of the current
transaction is noted by the rising edge of these signals.
CLK/TRG0–CLK/TRG3. External Clock/Timer Trigger (inputs, user-selectable Active
High or Low). These four pins correspond to the four counter/timer channels of the KIO.
In Counter mode, each active edge causes the downcounter to decrement. In Timer mode,
an active edge starts the timer.
CLKOUT. Clock Out (output). This output is a divide-by-two of the oscillator (XTAL)
input.
CLOCK. System Clock (input). This clock must be the same as (or a derivative of) the
CPU clock. If the CLKOUT is to be used as the system clock, then these two pins must be
connected together.
CS. Chip Select (input, Active Low). Used to activate the internal register decoding mech-
anism and allow the KIO to perform a data transfer to/from the CPU.
CTSA, CTSB. Clear to Send (inputs, Active Low). These signals are modem control sig-
nals for the serial channels. When programmed for Auto Enable, a Low on these pins
enables their respective transmitters. If not programmed as Auto Enable, these pins may
be used as general-purpose input signals.
D
the CPU and the KIO for programming and data transfer. The KIO also monitors the data
bus for RETI instructions to maintain its Interrupt Under Service (IUS) status.
DCDA, DCDB. Data Carrier Detect (inputs, Active Low). These signals are modem con-
trol signals for the serial channels. When programmed for Auto Enable, a Low on these
pins enables their respective receivers. If not programmed as Auto Enable, these pins may
be used as general-purpose input signals.
DTRA, DTRB. Data Terminal Ready (outputs, Active Low). These signals are modem
control signals for the serial channels. They follow the state programmed into their respec-
tive serial channels, and are multiplexed with Port C, bits 5 and 2, respectively.
0
–D
7
. Data Bus (bidirectional, Active High, 3-stated). Used for data exchanges between
Port B does not support Mode 2 operation and can only be used in
Mode 3 when Port A is programmed for Mode 2. BRDY is not
associated with Port B when it is operating in Mode 3.
Port B does not support Mode 2 operation, and can only be used in
Mode 3 when Port A is programmed for Mode 2. BSTB is not
associated with Port B when it is operating in Mode 3.
KIO Serial/Parallel Counter Timer
Z84C90
6