MPC8321EVRADDC Freescale Semiconductor, MPC8321EVRADDC Datasheet - Page 64

• Manufacturer Part Number: MPC8321EVRADDC
• Description: IC MPU PWRQUICC II 516-PBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC II PROr

Specifications of MPC8321EVRADDC

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 266MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 516-PBGA
• Processor Series: MPC8xxx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: MPC8323E-MDS-PB
• Maximum Clock Frequency: 266 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 16 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, SPI, UART
• Minimum Operating Temperature: - 40 C
• Core Size: 32 Bit
• Program Memory Size: 32KB
• Cpu Speed: 266MHz
• Embedded Interface Type: I2C, SPI, USB, UART
• Digital Ic Case Style: BGA
• No. Of Pins: 516
• Rohs Compliant: Yes
• Family Name: MPC83xx
• Device Core: PowerQUICC II Pro
• Device Core Size: 32b
• Frequency (max): 266MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1V
• Operating Supply Voltage (max): 1.05V
• Operating Supply Voltage (min): 0.95V
• Operating Temp Range: 0C to 105C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 516
• Package Type: TEBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Clocking
22 Clocking
Figure 43
The primary clock source for the MPC8323E can be one of two inputs, CLKIN or PCI_CLK, depending
on whether the device is configured in PCI host or PCI agent mode, respectively.
64
CFG_CLKIN_DIV
MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4
CLKIN
CLKIN
Crystal
shows the internal distribution of clocks within the MPC8323E.
MPC8323E
QUICC
Engine
System
PLL
PLL
Figure 43. MPC8323E Clock Subsystem
Divider (÷2)
PCI Clock
Clock
csb_clk
Unit
csb_clk to rest
of the device
e300c2 core
Core PLL
ddr_clk
lbc_clk
to local bus
controller
to DDR
memory
ce_clk to QUICC
Engine block
1
0
core_clk
Divider
/n
Divider
Clock
DDR
Clock
LBC
/2
3
MEMC_MCK
MEMC_MCK
LCLK[0:1]
PCI_CLK_OUT[0:2]
PCI_CLK/
PCI_SYNC_IN
PCI_SYNC_OUT
Freescale Semiconductor
Local Bus
Memory
Device
DDR
Memory
Device