MPC859TZP100A Freescale Semiconductor, MPC859TZP100A Datasheet - Page 39
MPC859TZP100A
Manufacturer Part Number
MPC859TZP100A
Description
IC MPU POWERQUICC 100MHZ 357PBGA
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC859DSLCVR50A.pdf
(96 pages)
Specifications of MPC859TZP100A
Processor Type
MPC8xx PowerQUICC 32-Bit
Speed
100MHz
Voltage
1.8V
Mounting Type
Surface Mount
Package / Case
357-PBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Available stocks
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Manufacturer
Quantity
Price
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Freescale Semiconductor
1
Num
P50
P51
P52
P53
P54
P55
P56
PSHT = 0. Otherwise, add PSHT times cycle time.
These synchronous timings define when the WAITx signals are detected in order to freeze (or relieve) the PCMCIA
current cycle. The WAITx assertion will be effective only if it is detected 2 cycles before the PSL timer expiration. See
PCMCIA Interface in the MPC866 PowerQUICC User’s Manual .
PSST = 1. Otherwise, add PSST times cycle time.
CLKOUT to PCOE, IORD, PCWE,
IOWR assert time (MAX = 0.00 x
B1 + 11.00)
CLKOUT to PCOE, IORD, PCWE,
IOWR negate time (MAX = 0.00 x
B1 + 11.00)
CLKOUT to ALE assert time (MAX
= 0.25 x B1 + 6.30)
CLKOUT to ALE negate time (MAX
= 0.25 x B1 + 8.00)
PCWE, IOWR negated to D(0:31)
invalid
WAITA and WAITB valid to
CLKOUT rising edge
x B1 + 8.00)
CLKOUT rising edge to WAITA and
WAITB invalid
2.00)
1
(MIN = 0.25 x B1 – 2.00)
Characteristic
1
(MIN = 0.00 x B1 +
1
(MIN = 0.00
MPC866/MPC859 Hardware Specifications, Rev. 2
Table 11. PCMCIA Timing (continued)
2.00
7.60
5.60
8.00
2.00
Min
—
—
33 MHz
11.00
11.00
13.80
15.60
Max
—
—
—
2.00
6.30
4.30
8.00
2.00
Min
—
—
40 MHz
11.00
11.00
12.50
14.30
Max
—
—
—
2.00
5.00
3.00
8.00
2.00
Min
—
—
50 MHz
11.00
11.00
11.30
13.00
Max
—
—
—
2.00
3.80
1.80
8.00
2.00
Min
—
—
66 MHz
Bus Signal Timing
11.00
11.00
10.00
11.80
Max
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
39