MPC880ZP133 Freescale Semiconductor, MPC880ZP133 Datasheet

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... To locate published errata or updates for this document, refer to the MPC875/MPC870 product summary page on our website listed on the back cover of this document or, contact your local Freescale sales office. © 2010 Freescale Semiconductor, Inc. All rights reserved. Document Number: MPC885EC Rev. 7, 07/2010 Contents 1 ...

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... Advanced on-chip emulation debug mode MPC885/MPC880 PowerQUICC Hardware Specifications, Rev Table 1. MPC885 Family Ethernet SCC SMC 10BaseT 10/100 Security USB ATM Support Engine 1 Serial ATM and UTOPIA interface 1 Serial ATM and UTOPIA interface Table 1) Freescale Semiconductor Yes No ...

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... Two fast Ethernet controllers (FEC)—Two 10/100 Mbps Ethernet/IEEE Std. 802.3™ CDMA/CS that interface through MII and/or RMII interfaces • System integration unit (SIU) — Bus monitor — Software watchdog MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7 Freescale Semiconductor 2 C can be relocated without RAM-based microcode Features 3 ...

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... Supports continuous mode transmission and reception on all serial channels — 8-Kbytes of dual-port RAM — Several serial DMA (SDMA) channels to support the CPM — Three parallel I/O registers with open-drain capability MPC885/MPC880 PowerQUICC Hardware Specifications, Rev GRACEFUL STOP TRANSMIT ) , ENTER HUNT Freescale Semiconductor ...

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... The USB function mode has the following features: – Four independent endpoints support control, bulk, interrupt, and isochronous data transfers. – CRC16 generation and checking – CRC5 checking – NRZI encoding/decoding with bit stuffing – 12- or 1.5-Mbps data rate MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7 Freescale Semiconductor Features 5 ...

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... Eight comparators: four operate on instruction address, two operate on data address, and two operate on data — Supports conditions: = ≠ < > — Each watchpoint can generate a break point internally. • Normal high and normal low power modes to conserve power MPC885/MPC880 PowerQUICC Hardware Specifications, Rev port Freescale Semiconductor ...

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... Bus Fast Ethernet Controller DMAs DMAs DMAs FIFOs 10/100 BaseT Media Access Control Parallel Interface MIII/RMII MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7 Freescale Semiconductor Figure 1. 8-Kbyte Unified 32-Entry ITLB Bus 8-Kbyte Data Cache Data MMU 32-Entry DTLB Slave/Master IF 4 Interrupt Parallel I/O ...

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... Time-Slot Assigner Serial Interface Serial Interface Figure 2. MPC880 Block Diagram System Interface Unit (SIU) Memory Controller Internal External Bus Interface Bus Interface Unit Unit System Functions PCMCIA-ATA Interface 8-Kbyte Dual-Port RAM Virtual IDMA and Serial DMAs 2 SMC1 SMC2 SPI I C Freescale Semiconductor ...

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... GND – 0 GND – 0.7 V Note refers to the clock period associated with the bus clock interface. interface Figure 3. Undershoot/Overshoot Voltage for V MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7 Freescale Semiconductor Table 3 displays the operating temperatures. Table 2. Maximum Tolerated Ratings Symbol V DDH V DDL VDDSYN ...

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... Environment Single-layer board (1s) Four-layer board (2s2p) Single-layer board (1s) Four-layer board (2s2p) — — — — — — Value Unit 0 °C 95 °C –40 °C 100 °C . Maximum Symbol Value Unit 2 °C θ θJMA θJMA θJMA R 17 θ θJC Ψ Ψ Freescale Semiconductor ...

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... V (except TMS, TRST, DSCK, and DSDI) in DDH Input leakage current (except TMS, TRST, DSCK and DSDI in pins) 4 Input capacitance MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7 Freescale Semiconductor Table 5. Power Dissipation (P CPU Bus Mode Typical Frequency 1:1 66 MHz 310 80 MHz 350 2:1 ...

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... DDSYN × PI/O, where PI/O is the power dissipation of the I/O D DDL DDL NOTE power dissipation is negligible. DDSYN , in °C can be obtained from the following equation: J × – are possible Symbol Min Max V 2.4 — — 0 standard. Freescale Semiconductor Unit V V ...

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... PBGA packages is strongly dependent on the board temperature; see Figure 4. Figure 4. Effect of Board Temperature Rise on Thermal Behavior MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7 Freescale Semiconductor θCA . For instance, the user can change the airflow around θCA Thermal Calculation and Measurement ...

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... The thermocouple wire is placed flat against the package case to avoid measurement errors caused by the cooling effects of the thermocouple wire. MPC885/MPC880 PowerQUICC Hardware Specifications, Rev × can be used to determine the junction temperature with Freescale Semiconductor ...

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... The MUR420 Schottky diodes control the maximum potential difference between the external bus and core power supplies on power up, and the 1N5820 diodes regulate the maximum potential difference on power down. MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7 Freescale Semiconductor http://www.jedec.org ) and PLL voltage (V DDL ...

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... MPC885/MPC880 PowerQUICC Hardware Specifications, Rev DDH MUR420 1N5820 power supply should be bypassed to ground DD and GND planes should be used. DD and GND circuits. Pull up all unused inputs or signals that will ).” SSSYN SSSYN1 V DDL DD Freescale Semiconductor and ...

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... CLKOUT pulse width low (MIN = 0.4 × MAX = 0.6 B1) B3 CLKOUT pulse width high (MIN = 0.4 × MAX = 0.6 B1) B4 CLKOUT rise time MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7 Freescale Semiconductor 66 MHz Min Max 40 66.67 20 33.33 Table 9. Bus Operation Timings 33 MHz Min Max Table 7 — ...

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... Freescale Semiconductor Unit ...

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... B26 CLKOUT rising edge to OE negated × (MAX = 0. 9.00) B27 A(0:31) and BADDR(28:30 asserted GPCM ACS = 10, TRLX = 1 (MIN = 1.25 × B1 – 2.00) MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7 Freescale Semiconductor Table 9. Bus Operation Timings (continued) 33 MHz Min Max 2 4.00 — 1.00 — ...

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... Freescale Semiconductor Unit — — ns — ns — ns — ns — ns — ns — ns — ns ...

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... UPM (MAX = 0.25 × 6.30) B31d CLKOUT falling edge to CS valid, as requested by control bit CST1 in the corresponding word in the UPM EBDF = 1 (MAX = 0.375 × 6.6) MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7 Freescale Semiconductor Table 9. Bus Operation Timings (continued) 33 MHz Min Max 38.40 — ...

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... Freescale Semiconductor Unit — ns — ns — ns — ns — ns — ns ...

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... B38 are specified to enable the freeze of the UPM output signals as described in 10 The AS signal is considered asynchronous to the CLKOUT. The timing B39 is specified in order to allow the behavior specified in Figure 24. MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7 Freescale Semiconductor Table 9. Bus Operation Timings (continued) 33 MHz Min Max 5.60 — ...

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... Maximum output delay specification. B Minimum output hold time. C Minimum input setup time specification. D Minimum input hold time specification. Figure 7 provides the timing for the external clock. CLKOUT MPC885/MPC880 PowerQUICC Hardware Specifications, Rev Figure 6. Control Timing Figure 7. External Clock Timing D B2 Freescale Semiconductor ...

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... Figure 8. Synchronous Output Signals Timing Figure 9 provides the timing for the synchronous active pull-up and open-drain output signals. CLKOUT TS, BB TA, BI TEA Figure 9. Synchronous Active Pull-Up Resistor and Open-Drain Outputs Signals Timing MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7 Freescale Semiconductor B8 B9 B8a B9 B8b B11 B12 B11a ...

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... It also applies to normal read accesses under the control of the user-programmable machine (UPM) in the memory controller. CLKOUT TA D[0:31] Figure 11. Input Data Timing in Normal Case MPC885/MPC880 PowerQUICC Hardware Specifications, Rev B16 B17 B16a B17a B16b B17 B16 B17 B18 B19 Freescale Semiconductor ...

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... GPCM factors. CLKOUT TS A[0:31] CSx OE WE[0:3] D[0:31] Figure 13. External Bus Read Timing (GPCM Controlled—ACS = 00) MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7 Freescale Semiconductor B20 B21 B11 B12 B8 B22 B25 B28 B18 Bus Signal Timing ...

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... Figure 14. External Bus Read Timing (GPCM Controlled—TRLX = 0, ACS = 10) CLKOUT TS A[0:31] CSx OE D[0:31] Figure 15. External Bus Read Timing (GPCM Controlled—TRLX = 0, ACS = 11) MPC885/MPC880 PowerQUICC Hardware Specifications, Rev B11 B12 B8 B22a B24 B25 B18 B11 B12 B22b B8 B22c B24a B25 B18 B23 B26 B19 B23 B26 B19 Freescale Semiconductor ...

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... CLKOUT B11 TS A[0:31] CSx OE D[0:31] Figure 16. External Bus Read Timing (GPCM Controlled—TRLX = 1, ACS = 10, ACS = 11) MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7 Freescale Semiconductor B12 B8 B22a B27 B27a B18 B22b B22c Bus Signal Timing B23 B26 B19 29 ...

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... GPCM factors. CLKOUT TS A[0:31] CSx WE[0:3] OE D[0:31] Figure 17. External Bus Write Timing (GPCM Controlled—TRLX = 0, CSNT = 0) MPC885/MPC880 PowerQUICC Hardware Specifications, Rev B11 B12 B8 B22 B25 B26 B8 B30 B23 B28 B29b B29 B9 Freescale Semiconductor ...

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... CLKOUT TS A[0:31] CSx WE[0:3] OE D[0:31] Figure 18. External Bus Write Timing (GPCM Controlled—TRLX = 0, CSNT = 1) MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7 Freescale Semiconductor B11 B12 B8 B22 B28b B28d B25 B26 B28a B28c B8 Bus Signal Timing B30a B30c B23 B29c B29g B29a B29f B9 31 ...

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... Bus Signal Timing CLKOUT B11 TS A[0:31] CSx WE[0:3] OE D[0:31] Figure 19. External Bus Write Timing (GPCM Controlled—TRLX = 1, CSNT = 1) MPC885/MPC880 PowerQUICC Hardware Specifications, Rev B12 B8 B22 B25 B26 B8 B28a B28c B30b B30d B28b B28d B23 B29e B29i B29d B29h B29b B9 Freescale Semiconductor ...

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... Figure 20 provides the timing for the external bus controlled by the UPM. CLKOUT A[0:31] CSx BS_A[0:3], BS_B[0:3] GPL_A[0:5], GPL_B[0:5] Figure 20. External Bus Timing (UPM-Controlled Signals) MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7 Freescale Semiconductor B8 B31a B31d B31 B34 B34a B34b B32a B32d B32 B35 ...

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... Figure 21. Asynchronous UPWAIT Asserted Detection in UPM-Handled Cycles Timing Figure 22 provides the timing for the asynchronous negated UPWAIT signal controlled by the UPM. CLKOUT B37 UPWAIT CSx BS_A[0:3], BS_B[0:3] GPL_A[0:5], GPL_B[0:5] Figure 22. Asynchronous UPWAIT Negated Detection in UPM-Handled Cycles Timing MPC885/MPC880 PowerQUICC Hardware Specifications, Rev B38 B38 Freescale Semiconductor ...

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... Figure 25 provides the timing for the asynchronous external master control signals negation. AS CSx, WE[0:3], OE, GPLx, BS[0:3] Figure 25. Asynchronous External Master—Control Signals Negation Timing MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7 Freescale Semiconductor B41 B42 B40 B39 B40 B43 Bus Signal Timing B22 ...

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... CLKOUT IRQx Figure 27. Interrupt Detection Timing for External Edge Sensitive Lines MPC885/MPC880 PowerQUICC Hardware Specifications, Rev Table 10. Interrupt Timing 1 4 × T I39 I40 I41 I43 I43 All Frequencies Unit Min Max 6.00 ns 2.00 ns 3.00 ns 3.00 ns — CLOCKOUT I42 Freescale Semiconductor ...

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... These synchronous timings define when the WAITx signals are detected in order to freeze (or relieve) the PCMCIA current cycle. The WAITx assertion will be effective only detected 2 cycles before the PSL timer expiration. See Chapter 16, “PCMCIA Interface,” in the MPC885 PowerQUICC™ Family Reference Manual . MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7 Freescale Semiconductor Table 11. PCMCIA Timing 33 MHz 40 MHz ...

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... PCMCIA access cycle timing for the external bus read. CLKOUT TS A[0:31] REG CE1/CE2 PCOE, IORD ALE D[0:31] Figure 28. PCMCIA Access Cycles Timing External Bus Read MPC885/MPC880 PowerQUICC Hardware Specifications, Rev P44 P46 P45 P48 P50 P52 P53 B18 P47 P49 P51 P52 B19 Freescale Semiconductor ...

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... ALE D[0:31] Figure 29. PCMCIA Access Cycles Timing External Bus Write Figure 30 provides the PCMCIA WAIT signals detection timing. CLKOUT WAITx Figure 30. PCMCIA WAIT Signals Detection Timing MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7 Freescale Semiconductor P44 P46 P45 P48 P50 P52 P53 B8 P55 ...

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... Figure 32. PCMCIA Input Port Timing 40 MHz 66 MHz 80 MHz Min Max Min Max Min Max — 19.00 — 19.00 — 19.00 21.70 — 14.40 — 12.40 5.00 — 5.00 — 5.00 1.00 — 1.00 — 1.00 Freescale Semiconductor Unit ns — ns — ns — ns ...

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... DSCK Figure 34 provides the timing for the debug port. DSCK DSDI DSDO MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7 Freescale Semiconductor Table 13. Debug Port Timing Characteristic D61 D62 D61 D63 Figure 33. Debug Port Clock Input Timing ...

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... Freescale Semiconductor ...

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... Figure 36. Reset Timing—Data Bus Weak Drive During Configuration Figure 37 provides the reset timing for the debug port configuration. CLKOUT SRESET DSCK, DSDI Figure 37. Reset Timing—Debug Port Configuration MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7 Freescale Semiconductor R71 R76 R73 R74 R75 R69 R79 ...

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... Figure All Frequencies Min Max 100.00 — 40.00 — 0.00 10.00 5.00 — 25.00 — — 27.00 0.00 — — 20.00 100.00 — 40.00 — — 50.00 — 50.00 — 50.00 50.00 — 50.00 — J83 J84 Freescale Semiconductor 41. Unit ...

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... Figure 39. JTAG Test Access Port Timing Diagram TCK TRST TCK Output Signals Output Signals Output Signals Figure 41. Boundary Scan (JTAG) Timing Diagram MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7 Freescale Semiconductor J85 J86 J87 J88 J91 J90 Figure 40. JTAG TRST Timing Diagram J92 J93 IEEE 1149.1 Electrical Specifications J89 ...

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... MPC885/MPC880 PowerQUICC Hardware Specifications, Rev Figure 42 Table 16. PIP/PIO Timing Characteristic through Figure 46. All Frequencies Min Max 0 — 0 — 1.5 — 1 clk – — 2 — 5 — — 4.5 2 — 15 — 7.5 — — Freescale Semiconductor Unit ns clk clk ns clk clk clk clk ...

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... STBI (Input) Figure 43. PIP Tx (Interlock Mode) Timing Diagram DATA-IN STBI (Input) STBO (Output) Figure 44. PIP Rx (Pulse Mode) Timing Diagram DATA-OUT STBO (Output) STBI (Input) Figure 45. PIP TX (Pulse Mode) Timing Diagram MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7 Freescale Semiconductor CPM Electrical Characteristics ...

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... Port C interrupt pulse width low (edge-triggered mode) 36 Port C interrupt minimum time between active edges Figure 47 shows the port C interrupt detection timing. Port C (Input) MPC885/MPC880 PowerQUICC Hardware Specifications, Rev Table 17. Port C Interrupt Timing Characteristic 35 Figure 47. Port C Interrupt Detection Timing 30 33.34 MHz Unit Min Max 55 — — Freescale Semiconductor ...

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... TA assertion to rising edge of the clock setup time (applies to external TA) 1 Applies to high-to-low mode (EDM = 1). CLKO (Output) DREQ (Input) Figure 48. IDMA External Requests Timing Diagram MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7 Freescale Semiconductor Figure 48 Table 18. IDMA Controller Timing Characteristic 1 40 CPM Electrical Characteristics tthrough Figure 51 ...

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... CPM Electrical Characteristics CLKO (Output) TS (Output) R/W (Output) DATA TA (Input) SDACK Figure 49. SDACK Timing Diagram—Peripheral Write, Externally-Generated TA CLKO (Output) TS (Output) R/W (Output) DATA TA (Output) SDACK Figure 50. SDACK Timing Diagram—Peripheral Write, Internally-Generated TA MPC885/MPC880 PowerQUICC Hardware Specifications, Rev Freescale Semiconductor ...

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... Num 50 BRGO rise and fall time 51 BRGO duty cycle 52 BRGO cycle BRGOX Figure 52. Baud Rate Generator Timing Diagram MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7 Freescale Semiconductor 42 Table 19. Baud Rate Generator Timing Characteristic CPM Electrical Characteristics 45 Figure 52 ...

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... Figure 54 Table 21. SI Timing Characteristic Figure 53. All Frequencies Min Max 10 — 1 — 2 — 3 — through Figure 58. All Frequencies Min Max — SYNCCLK/2 — — — 15.00 20.00 — 35.00 — — 15.00 Freescale Semiconductor Unit ns clk clk clk ns Unit MHz ...

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... These specs are valid for IDL mode only. 3 Where P = 1/CLKOUT. Thus for a 25-MHz CLKO1 rate ns. 4 These strobes and TxD on the first bit of the frame become valid after L1CLK edge or L1SYNC, whichever comes later. MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7 Freescale Semiconductor Table 21. SI Timing (continued) Characteristic ...

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... CPM Electrical Characteristics L1RCLK ( (Input) 71 L1RCLK ( (Input) L1RSYNC (Input) 73 L1RXD (Input) L1ST(4-1) (Output) Figure 54. SI Receive Timing Diagram with Normal Clocking (DSC = 0) MPC885/MPC880 PowerQUICC Hardware Specifications, Rev 71a 72 RFSD BIT0 Freescale Semiconductor ...

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... L1RCLK ( (Input) 82 L1RCLK ( (Input) 75 L1RSYNC (Input L1RXD (Input) 76 L1ST(4-1) (Output) L1CLKO (Output) Figure 55. SI Receive Timing with Double-Speed Clocking (DSC = 1) MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7 Freescale Semiconductor 72 83a RFSD=1 77 BIT0 78 84 CPM Electrical Characteristics 79 55 ...

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... CPM Electrical Characteristics L1TCLK ( (Input) 71 L1TCLK ( (Input) 73 L1TSYNC (Input) L1TXD (Output) L1ST(4-1) (Output) Figure 56. SI Transmit Timing Diagram (DSC = 0) MPC885/MPC880 PowerQUICC Hardware Specifications, Rev TFSD 80a BIT0 Freescale Semiconductor ...

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... L1RCLK ( (Input) L1RCLK ( (Input) L1RSYNC (Input) 73 L1TXD BIT0 (Output) 80 78a L1ST(4-1) (Output) 84 L1CLKO (Output) Figure 57. SI Transmit Timing with Double Speed Clocking (DSC = 1) MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7 Freescale Semiconductor 72 83a 82 TFSD CPM Electrical Characteristics 79 57 ...

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... CPM Electrical Characteristics MPC885/MPC880 PowerQUICC Hardware Specifications, Rev Figure 58. IDL Timing Freescale Semiconductor ...

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... The ratios SyncCLK/RCLK1 and SyncCLK/TCLK1 must be greater than or equal to 3/1. 2 Also applies to CD and CTS hold time when they are used as external sync signals MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7 Freescale Semiconductor Table 22. NMSI External Clock Timing 1 2 Table 23. NMSI Internal Clock Timing ...

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... Figure 59. SCC NMSI Receive Timing Diagram TCLK1 102 TxD1 (Output) RTS1 (Output) CTS1 (Input) CTS1 (SYNC Input) Figure 60. SCC NMSI Transmit Timing Diagram MPC885/MPC880 PowerQUICC Hardware Specifications, Rev 102 101 100 107 102 101 100 103 105 104 108 107 104 107 Freescale Semiconductor ...

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... TCLK1 clock period 131 TXD1 active delay (from TCLK1 rising edge) 132 TXD1 inactive delay (from TCLK1 rising edge) 133 TENA active delay (from TCLK1 rising edge) MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7 Freescale Semiconductor 102 101 100 103 104 107 105 Figure 61 ...

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... RCLK1 RxD1 (Input) RENA(CD1) (Input) Figure 63. Ethernet Receive Timing Diagram MPC885/MPC880 PowerQUICC Hardware Specifications, Rev Table 24. Ethernet Timing (continued) Characteristic 2 2 120 121 124 125 All Frequencies Min Max 10 50 — 20 — 20 121 123 Last Bit 126 127 Freescale Semiconductor Unit ...

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... SMTXD active delay (from SMCLK falling edge) 154 SMRXD/SMSYNC setup time 155 RXD1/SMSYNC hold time 1 SyncCLK must be at least twice as fast as SMCLK. MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7 Freescale Semiconductor 128 121 132 Figure Table 25. SMC Transparent Timing Characteristic CPM Electrical Characteristics ...

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... Fall time output MPC885/MPC880 PowerQUICC Hardware Specifications, Rev 152 151 151A 150 Note 1 154 155 154 155 Figure 66 Table 26. SPI Master Timing Characteristic 153 and Figure 67. All Frequencies Min Max 4 1024 2 512 15 — 0 — — — — 15 — 15 Freescale Semiconductor Unit t cyc t cyc ...

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... SPICLK ( (Output) 163 162 SPIMISO msb (Input) 167 SPIMOSI (Output) Figure 67. SPI Master ( Timing Diagram MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7 Freescale Semiconductor 167 166 160 167 162 166 Data lsb 165 164 Data lsb 167 166 160 167 ...

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... Table 27. SPI Slave Timing Characteristic 172 182 181 170 181 182 180 Data lsb 179 181 182 Data lsb Figure 69. All Frequencies Min Max 2 — 15 — 15 — 1 — 1 — 20 — 20 — — 50 171 174 178 Undef msb msb Freescale Semiconductor Unit t cyc cyc t cyc ...

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... High period of SCL 205 Start condition setup time 206 Start condition hold time 207 Data hold time 208 Data setup time 209 SDL/SCL rise time MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7 Freescale Semiconductor 172 170 182 181 181 182 180 msb Data 179 176 ...

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... Freescale Semiconductor Unit ns μs Unit ...

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... Frequency U2 UTPB, SOC, Rxclav, and Txclav active delay U3 UTPB_AUX, SOC_Aux, RxEnb, TxEnb, RxAddr, and TxAddr setup time U4 UTPB_AUX, SOC_Aux, RxEnb, TxEnb, RxAddr, and TxAddr hold time MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7 Freescale Semiconductor UTOPIA AC Electrical Specifications Direction Min Max Unit Output 4 ...

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... High-Z at MPHY RxEnb UTPB SOC Figure 72 shows signal timings during UTOPIA transmit operations. UtpClk U2 5 PHSEL n TxClav High-Z at MPHY TxEnb UTPB SOC MPC885/MPC880 PowerQUICC Hardware Specifications, Rev Figure 71. UTOPIA Receive Timing Figure 72. UTOPIA Transmit Timing High-Z at MPHY High-Z at Multi-PHYPHY Freescale Semiconductor ...

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... M4 MII_RX_CLK pulse width low M1_RMII RMII_RXD[1:0], RMII_CRS_DV, RMII_RX_ERR to RMII_REFCLK setup M2_RMII RMII_REFCLK to RMII_RXD[1:0], RMII_CRS_DV, RMII_RX_ERR hold MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7 Freescale Semiconductor Table 33 lists the USB interface timings. Characteristic 1 1%. – Table 34. MII Receive Signal Timing Characteristic USB Electrical Characteristics ...

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... M7 MII_TX_CLK and RMII_REFCLK pulse width high M8 MII_TX_CLK and RMII_REFCLK pulse width low MPC885/MPC880 PowerQUICC Hardware Specifications, Rev Table 35. MII Transmit Signal Timing Characteristic M4 Min Max Unit 5 — ns — — — ns 35% 65% MII_TX_CLK or RMII_REFCLK period 35% 65% MII_TX_CLK or RMII_REFCLK period Freescale Semiconductor ...

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... M11 MII_MDC falling edge to MII_MDIO output valid (max prop delay) M12 MII_MDIO (input) to MII_MDC rising edge setup M13 MII_MDIO (input) to MII_MDC rising edge hold MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7 Freescale Semiconductor Table 36. MII Async Inputs Signal Timing Characteristic M9 Characteristic FEC Electrical Characteristics ...

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... MII serial management channel timing diagram. MII_MDC (Output) MII_MDIO (Output) MII_MDIO (Input) Figure 76. MII Serial Management Channel Timing Diagram MPC885/MPC880 PowerQUICC Hardware Specifications, Rev Characteristic M14 M10 M11 M12 M13 Min Max Unit 40% 60% MII_MDC period 40% 60% MII_MDC period MM15 Freescale Semiconductor ...

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... MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7 Freescale Semiconductor Mechanical Data and Ordering Information Temperature (Tj) Frequency (MHz) 0°C to 95° 133 -40°C to 100°C 66 133 Order Number KMPC885ZP66 KMPC880ZP66 MPC885ZP66 MPC880ZP66 KMPC885ZP80 KMPC880ZP80 MPC885ZP80 MPC880ZP80 KMPC885ZP133 KMPC880ZP133 MPC885ZP133 MPC880ZP133 KMPC885CZP66 KMPC880CZP66 MPC885CZP66 MPC880CZP66 KMPC885CZP133 KMPC880CZP133 MPC885CZP133 MPC880CZP133 75 ...

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... GND VDDH CLKOUT D26 D24 D25 IPA2 D31 D7 D29 VDDL VSSSYN IPA3 IPA6 D30 AS MODCK1 EXTAL RSTCONF IPA7 IPA4 IPA5 IRQ4 OP1 BADDR28 TEXP WAIT_B VSSSYN1 IPA1 ALEA OP0 BADDR29 HRESET PORESETVDDLSYN IPA0 BADDR30 MODCK2 EXTCLK XTAL SRESET WAIT_A Freescale Semiconductor ...

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... N4 IRQ1 P3 IRQ7 P4 CS[0:5] B14, C14, A15, D14, C16, A16 CS6, CE1_B D15 CS7, CE2_B B16 MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7 Freescale Semiconductor Table 39. Pin Assignments Pin Number Mechanical Data and Ordering Information Type Bidirectional Three-state Bidirectional Three-state Bidirectional Three-state Bidirectional Three-state ...

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... Output Output Output Output Output Output Output Output Bidirectional Bidirectional Output Input Input Open-drain Open-drain Analog output Analog input (3.3 V only) Output Input (3.3 V only) Output Output Output Output Input Input Input Input Input Input Input Input Input Input Freescale Semiconductor ...

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... W15 PA7, CLK1, L1RCLKA, V14 BRGO1, TIN1 PA6, CLK2, TOUT1 U13 PA5, CLK3, L1TCLKA, W13 BRGO2, TIN2 MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7 Freescale Semiconductor Table 39. Pin Assignments (continued) Pin Number Mechanical Data and Ordering Information Type Bidirectional Three-state Bidirectional Bidirectional Three-state ...

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... Bidirectional (Optional: open-drain) Bidirectional (Optional: open-drain) Bidirectional (Optional: open-drain) Bidirectional (Optional: open-drain) Bidirectional (Optional: open-drain) Bidirectional (Optional: open-drain) Bidirectional (Optional: open-drain) Bidirectional (Optional: open-drain) Bidirectional (Optional: open-drain) Bidirectional (Optional: open-drain) Bidirectional (Optional: open-drain) Bidirectional (Optional: open-drain) Bidirectional (Optional: open-drain) Freescale Semiconductor ...

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... T2 PD9, TXD4, UTPCLK U2 PD8, RXD4, MII-MDC, R3 RMII-MDC PD7, RTS3, UTPB4 W3 PD6, RTS4, UTPB5 W5 MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7 Freescale Semiconductor Table 39. Pin Assignments (continued) Pin Number Mechanical Data and Ordering Information Type Bidirectional (Optional: open-drain) Bidirectional (Optional: open-drain) Bidirectional Bidirectional Bidirectional ...

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... Bidirectional (Optional: open-drain) Bidirectional (Optional: open-drain) Bidirectional (Optional: open-drain) Bidirectional (Optional: open-drain) Bidirectional (Optional: open-drain) Bidirectional (Optional: open-drain) Bidirectional (Optional: open-drain) Bidirectional (Optional: open-drain) Bidirectional (Optional: open-drain) Bidirectional (Optional: open-drain) Bidirectional (Optional: open-drain) Bidirectional (Optional: open-drain) Bidirectional Freescale Semiconductor ...

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... F14, F15, G5, G14, H6, H15, J6, J14, K5, K6, K14, L6, L14, L15, M5, M6, M14, N6, N15, P5, P6, P8, P9, P10, P11, P12, P14, P15, R5, R7, R8, R11, R13, R14 N/C N17 1 ESAR mode only. MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7 Freescale Semiconductor Table 39. Pin Assignments (continued) Pin Number Mechanical Data and Ordering Information Type Bidirectional Input Input ...

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... INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M—1994. 3. MAXIMUM SOLDER BALL DIAMETER MEASURED PARALLEL TO DATUM A. 4. DATUM A, THE SEATING PLANE, IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. Figure 78. Mechanical Dimensions and Bottom Surface Nomenclature of the PBGA Package MPC885/MPC880 PowerQUICC Hardware Specifications, Rev Freescale Semiconductor ...

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... Changed the pin descriptions per the June 22 spec. 0.5 5/2003 Changed some more typos, put in the phsel and phreq pins. Corrected the USB timing. MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7 Freescale Semiconductor Table 40. Document Revision History Changes “Bus Operation Timings,” changed the following: Section 10, “Bus Signal ...

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... Added pinout and pinout assignments table. Added the USB timing to Section 14. Added the Reduced MII to Section 15. Removed the Data Parity. Made some changes to the Features list. 0 02/2003 Initial revision. MPC885/MPC880 PowerQUICC Hardware Specifications, Rev Changes , V , and GND show up on the DDL DDH Freescale Semiconductor ...

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... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...