MPC8245LZU333D Freescale Semiconductor, MPC8245LZU333D Datasheet - Page 2

• Manufacturer Part Number: MPC8245LZU333D
• Description: IC MPU 32BIT 333MHZ 352-TBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC IIr

Specifications of MPC8245LZU333D

• Processor Type: MPC82xx PowerQUICC II 32-bit
• Speed: 333MHz
• Voltage: 2V
• Mounting Type: Surface Mount
• Package / Case: 352-TBGA
• Core Size: 32 Bit
• Program Memory Size: 32KB
• Cpu Speed: 333MHz
• Embedded Interface Type: I2C
• Digital Ic Case Style: TBGA
• No. Of Pins: 352
• Supply Voltage Range: 1.9V To 2.2V
• Rohs Compliant: No
• Family Name: MPC82XX
• Device Core: PowerPC
• Device Core Size: 64b
• Frequency (max): 333MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 2/2.1/3.3V
• Operating Supply Voltage (max): 2.2/3.465V
• Operating Supply Voltage (min): 1.9/3.135V
• Operating Temp Range: 0C to 105C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 352
• Package Type: TBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Not Compliant

Technical Specifications
G2 Processor Core
• High-performance, superscalar processor core
• Floating-point unit, integer, load/store,
• 16 KB instruction cache, 16 KB data cache
• Lockable portion of L1 cache
• Dynamic power management
• Software-compatible with the Freescale
On-Chip Peripheral Logic
• Memory interface
• 133 MHz memory bus capability
• Programmable timing supporting SDRAM
• High-bandwidth bus (32-bit/64-bit data bus)
• Supports one to eight banks of 16-, 64-,
• Supports 1 MB to 2 GB DRAM memory
• Contiguous memory mapping
• 272 MB of ROM space
• 8-, 16-, 32- or 64-bit ROM
• Supports bus-width writes to flash
MPC8245 Integrated Host Processor
CPU Speeds—Internal
CPU Bus Dividers
Memory Bus Dividers
PCI Interface
Memory Interface
Instructions Per Clock
L1 Cache
Typical Power Dissipation (est.)
Package
Process
Voltage
Dhrystone (2.1) MIPS
603e Processor Core Functional Units
Peripheral Logic Functional Units
system register and branch processing unit
processor families built on Power
Architecture technology
to DRAM
128-, 256- or 512-bit SDRAM
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service
names are the property of their respective owners. The Power Architecture and Power.org word marks and the Power
and Power.org logos and related marks are trademarks and service marks licensed by Power.org.
© Freescale Semiconductor, Inc. 2007
Document Number: MPC8245FACT
REV 5
I
2.8W @ 400 MHZ (with FPU on and @ 2.0V)
2
• Read-modify-write parity support (selectable)
• ECC support (selectable)
• SDRAM, DRAM buffer data-path
• Error injection/capture on data-path
• Low voltage transistor transistor logic
• PortX: 8-, 16-, 32- or 64-bit
32-bit PCI Interface Operating
up to 66 MHz
• PCI 2.2V compatible
• PCI 5.0V tolerant
• Support for PCI-locked accesses
• Support for accesses to all PCI
• Selectable big- or little-endian operation
• Store gathering of processor-to-PCI writes
• Memory prefetching of PCI read accesses
• Parity support (selectable)
• Selectable hardware-enforced coherency
• PCI bus arbitration unit
1.3W @ 266 MHz (with FPU on and @ 1.8V)
O, I
Integer, floating-point, branch processing,
(LVTTL) compatible
general-purpose I/O port uses ROM
controller interface with address strobe
to memory
address spaces
and PCI-to-memory writes
(five request/grant pairs)
2.0, 2.5, 3.0, 3.5, 4.0, 4.5, 5.0, 5.5, 6.0
load/store, PCI, DMA, memory control
64-bit (up to 133 MHz) + 8-bit parity
2
C, EPIC, ATU, PCI and memory clocks,
3.3V I/O, (1.8V–2.0V internal)
ECC controller x2 DUART
32-bit (up to 66 MHz)
1.0, 1.5, 2.0, 2.5, 3.0
266 MHz–400 MHz
0.25µ 5LM CMOS
16 KB instruction
760 @ 400 MHz
3 (2 + branch)
16 KB data
352 TBGA
Learn More:
PCI Agent Mode Capability
• Dual address translation unit (ATU)
• Run-time register access
• PCI configuration register access
Two-Channel Integrated DMA Controller
• Supports direct or chaining modes
• Scatter gather
• Interrupt on completed segment, chain
• Local to local memory
• PCI to PCI memory
• PCI to local memory
• Local to PCI memory
• Message unit
• I
• I
• Embedded programmable interrupt
• Five hardware interrupts (IRQs) or
• Four programmable timers
Integrated PCI Bus and SDRAM Clock
Generation Programmable Memory and
PCI Bus Drivers Debug Features
• Watchpoint monitor
• Memory attribute and PCI attribute signals
• JTAG/COP (common on-board processor)
Dual UART
Contact Information
Freescale offers user’s manuals,
application notes and sample code for
all of its communications processors.
Local support for these products is also
provided. Information can be found at
www.freescale.com/powerarchitecture.
For current information about Freescale
products and documentation, please visit
www.freescale.com.
and error
controller (EPIC)
16 serial interrupts
for in-circuit hardware debugging
2
2
O message controller
C controller
Two door-bell registers
Inbound and outbound messaging registers
Full master/slave support