MC68030FE25C Freescale Semiconductor, MC68030FE25C Datasheet - Page 7

• Manufacturer Part Number: MC68030FE25C
• Description: IC MPU 32BIT ENHANCED 132-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68030FE25C

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-CQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: CQUAD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

M O T O R O L A
All microprocessors of the M68000 Family support instruction tracing (via the T0 status bit in the
MC68EC030) where each instruction executed is followed by a trap to a user-defined trace routine. The
MC68EC030, like the MC68030 and MC68040, also has the capability to trace only on change-of-flow
instructions (branch, jump, subroutine call and return, etc.) using the T1 status bit. These features are
important for software program development and debug.
The vector base register (VBR) is used to determine the run-time location of the exception vector table in
memory; thus, each separate vector table for each process or task can properly manage exceptions
independent of each other.
The M68000 Family processors distinguish address spaces as supervisor/user, program/data, and CPU
space. These five combinations are specified by the function code pins (FC0/FC1/FC2) during bus
cycles, indicating the particular address space. Using the function codes, the memory subsystem
(hardware) can distinguish between supervisor accesses and user accesses as well as program accesses,
data accesses, and CPU space accesses. To support the full privileges of the supervisor, the alternate
function code registers allow the supervisor to specify the function code for an access by appropriately
preloading the SFC/DFC registers.
The cache registers allow supervisor software manipulation of the on-chip instruction and data caches.
Control and status accesses to the caches are provided by the cache control register (CACR); the cache
address register (CAAR) specifies the address for those cache control functions that require an address.
The access control registers are accessible by the supervisor only. The access control registers are used
to define two memory spaces with caching restrictions. The ACU status register (ACUSR) is used to show
the result of PTEST operations on the ACU.
Seven basic data types are supported by the MC68EC030:
• Bits
• Bit Fields (String of consecutive bits, 1–32 bits long)
• BCD Digits (Packed: 2 digits/byte, Unpacked: 1 digit/byte)
• Byte Integers (8 bits)
• Word Integers (16 bits)
• Long-Word Integers (32 bits)
• Quad-Word Integers (64 bits)
DATA TYPES AND ADDRESSING MODES
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68EC030 TECHNICAL DATA
Go to: www.freescale.com
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