MC68MH360AI33L Freescale Semiconductor, MC68MH360AI33L Datasheet - Page 75

• Manufacturer Part Number: MC68MH360AI33L
• Description: IC MPU QUICC 33MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360AI33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

5.2 Transmit Buffer Descriptor
Figure 5-3 shows the transmit buffer descriptor.
Table 5-2 describes the individual fields of a transmit buffer descriptor. Boldfaced entries
must be initialized by the user.
0
1
2
3
4
5
Field
OFFSET + 0
OFFSET + 2
OFFSET + 4
OFFSET + 6
Notes: Entries in boldface must be initialized by the user.
Name
R
—
W
I
L
TC
For the 68360, the bit numbering is reversed. See Appendix A for more information.
Table 5-2. Transmit Buffer Descriptor (TxBD) Field Descriptions
R
0
Ready
0 The data buffer associated with this buffer descriptor is not ready for transmission. The user
1 The data buffer, which has been prepared for transmission by the user, has not been
—
Wrap (final buffer descriptor in table)
0 This is not the last buffer descriptor in the TxBD table.
1 This is the last descriptor in the Tx buffer descriptor table. After this buffer is used, the CPM
Interrupt
0 No interrupt is generated after this buffer has been serviced.
1 TXB in the circular interrupt table entry is set when the controller services this buffer. This bit
Last
0 This is not the last buffer in the frame.
1 This is the last buffer in the current frame.
Tx CRC (HDLC mode only). This bit is valid only when L = 1; otherwise, it is ignored.
0 Transmit the closing flag after the last data byte. This setting can be used for testing purposes
1 Transmit the CRC sequence after the last data byte.
can manipulate this buffer descriptor or its associated data buffer. The CPM clears this bit
after the buffer has been transmitted or after an error condition is encountered.
transmitted or is being transmitted. If R = 1, the user cannot write to fields of this buffer
descriptor.
transmits data from the first buffer descriptor in the table (the buffer descriptor pointed to by
TBASE). The number of TxBDs in this table is programmable and is determined only by the
wrap bit and the overall space constraints of the dual-ported RAM.
can cause an interrupt (if enabled).
to send an erroneous CRC after the data.
—
1
Freescale Semiconductor, Inc.
Figure 5-3. Transmit Buffer Descriptor (TxBD)
For More Information On This Product,
W
2
3
I
Go to: www.freescale.com
Chapter 5. Buffer Descriptors
L
4
TC
5
CM
Tx DATA BUFFER POINTER
6
DATA LENGTH
—
Description
7
UB
8
—
9
10
—
11
—
12
13
PAD
14
15