MPC603RRX266TC Freescale Semiconductor, MPC603RRX266TC Datasheet - Page 3

• Manufacturer Part Number: MPC603RRX266TC
• Description: IC MPU 32BIT 266MHZ 255-CBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC603RRX266TC

• Processor Type: MPC603e PowerPC 32-Bit
• Speed: 266MHz
• Voltage: 2.5V
• Mounting Type: Surface Mount
• Package / Case: 255-CBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

supports block address translation through the use of two independent instruction and data block address
translation (IBAT and DBAT) arrays of four entries each. Effective addresses are compared simultaneously
with all four entries in the BAT array during block translation. In accordance with the PowerPC architecture,
if an effective address hits in both the TLB and BAT array, the BAT translation takes priority.
The 603e has a selectable 32- or 64-bit data bus and a 32-bit address bus. The 603e interface protocol allows
multiple masters to compete for system resources through a central external arbiter. The 603e provides a
three-state coherency protocol that supports the exclusive, modiÞed, and invalid cache states. This protocol
is a compatible subset of the MESI (modiÞed/exclusive/shared/invalid) four-state protocol and operates
coherently in systems that contain four-state caches. The 603e supports single-beat and burst data transfers
for memory accesses, and supports memory-mapped I/O.
The 603e uses an advanced, 2.5/3.3-V CMOS process technology and maintains full interface compatibility
with TTL devices. The PID7t-603e is offered in both PBGA and CBGA packages. The CBGA package
supports speed bins of 200 MHz, 266 MHz, and 300 MHz. The PBGA package is a pin-compatible drop in
replacement for the CBGA; however this package only supports speeds up to 200 MHz.
1.2 Features
This section summarizes features of the 603eÕs implementation of the PowerPC architecture. Major features
of the 603e are as follows:
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High-performance, superscalar microprocessor
Ñ As many as three instructions issued and retired per clock
Ñ As many as Þve instructions in execution per clock
Ñ Single-cycle execution for most instructions
Ñ Pipelined FPU for all single-precision and most double-precision operations
Five independent execution units and two register Þles
Ñ BPU featuring static branch prediction
Ñ A 32-bit IU
Ñ Fully IEEE 754-compliant FPU for both single- and double-precision operations
Ñ LSU for data transfer between data cache and GPRs and FPRs
Ñ SRU that executes condition register (CR), special-purpose register (SPR) instructions, and
Ñ Thirty-two GPRs for integer operands
Ñ Thirty-two FPRs for single- or double-precision operands
High instruction and data throughput
Ñ Zero-cycle branch capability (branch folding)
Ñ Programmable static branch prediction on unresolved conditional branches
Ñ Instruction fetch unit capable of fetching two instructions per clock from the instruction cache
Ñ A six-entry instruction queue that provides lookahead capability
Ñ Independent pipelines with feed-forwarding that reduces data dependencies in hardware
Ñ 16-Kbyte data cacheÑfour-way set-associative, physically addressed; LRU replacement
integer add/compare instructions
algorithm
Freescale Semiconductor, Inc.
For More Information On This Product,
PID7t-603e Hardware Specifications
Go to: www.freescale.com
Features
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