MC68020FE25E Freescale Semiconductor, MC68020FE25E Datasheet - Page 100

• Manufacturer Part Number: MC68020FE25E
• Description: IC MICROPROCESSOR 32BIT 132CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68020FE25E

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-CQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

5.4.3 Coprocessor Communication Cycles
The MC68020/EC020 coprocessor interface provides instruction-oriented communication
between the processor and as many as eight coprocessors. Coprocessor accesses use
the MC68020/EC020 bus protocol except that the address bus supplies access
information rather than a 32-bit address. The CPU space type field (A19–A16) for a
coprocessor operation is 0010. A15–A13 contain the coprocessor identification number
(CpID), and A5–A0 specify the coprocessor interface register to be accessed. The
memory management unit of an MC68020/EC020 system is always identified by a CpID of
zero and has an extended register select field (A7–A0) in CPU space 0001 for use by the
CALLM and RTM access level checking mechanism. Refer to Section 9 Applications
Information for more details.
5.5 BUS EXCEPTION CONTROL CYCLES
The MC68020/EC020 bus architecture requires assertion of DSACK1/DSACK0 from an
external device to signal that a bus cycle is complete. DSACK1/DSACK0 or AVEC is not
asserted if:
External circuitry can assert B E R R when no device responds by asserting
DSACK1/DSACK0 or A V E C within an appropriate period of time after the processor
asserts AS. Assertion of BERR allows the cycle to terminate and the processor to enter
exception processing for the error condition.
HALT is also used for bus exception control. HALT can be asserted by an external device
for debugging purposes to cause single bus cycle operation or can be asserted in
combination with BERR to cause a retry of a bus cycle in error.
To properly control termination of a bus cycle for a retry or a bus error condition,
DSACK1/DSACK0, BERR, and HALT can be asserted and negated with the rising edge of
the MC68020/EC020 clock. This procedure ensures that when two signals are asserted
simultaneously, the required setup time (#47A) and hold time (#47B) for both of them is
met for the same falling edge of the processor clock. (Refer to Section 10 Electrical
Characteristics for timing requirements.) This or some equivalent precaution should be
designed into the external circuitry that provides these signals.
MOTOROLA
• The external device does not respond,
• No interrupt vector is provided, or
• Various other application-dependent errors occur.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
M68020 USER’S MANUAL
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