MPC8541EVTAQF Freescale Semiconductor, MPC8541EVTAQF Datasheet - Page 82

• Manufacturer Part Number: MPC8541EVTAQF
• Description: IC MPU POWERQUICC III 783-FCPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8541EVTAQF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 1.3V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Development Tools By Supplier: RDK-IDM-SBC
• Maximum Clock Frequency: 1000 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• I/o Voltage: 2.5 V, 3.3 V
• Minimum Operating Temperature: 0 C
• For Use With: MPC8548CDS - DEV TOOLS CDS FOR 8548CWH-PPC-8540N-VE - KIT EVAL SYSTEM MPC8540
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

System Design Information
82
2. Populate this with a 10 Ω resistor for short-circuit/current-limiting protection.
3. The KEY location (pin 14) is not physically present on the COP header.
4. Although pin 12 is defined as a No-Connect, some debug tools may use pin 12 as an additional GND pin for
5. This switch is included as a precaution for BSDL testing. The switch should be open during BSDL testing to avoid
6. Asserting SRESET causes a machine check interrupt to the e500 core.
1. The COP port and target board should be able to independently assert HRESET and TRST to the processor
Notes:
COP Connector
improved signal integrity.
accidentally asserting the TRST line. If BSDL testing is not being performed, this switch should be closed or removed.
Physical Pinout
in order to fully control the processor as shown here.
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
13
15
11
1
1
3
5
7
9
Board Sources
No pin
KEY
From Target
10
12
16
4
6
8
2
(if any)
14
13
15
10
12
16
11
SRESET
HRESET
4
6
5
8
9
1
3
7
2
3
COP_CHKSTP_IN
COP_CHKSTP_OUT
COP_VDD_SENSE
COP_TMS
COP_TDO
COP_TDI
COP_TCK
COP_SRESET
COP_TRST
COP_HRESET
Figure 52. JTAG Interface Connection
NC
NC
NC
4
2
5
10 kΩ
10 Ω
10 kΩ
10 kΩ
10 kΩ
10 kΩ
10 kΩ
10 kΩ
10 kΩ
10 kΩ
OV
DD
SRESET
HRESET
TRST
CKSTP_OUT
CKSTP_IN
TMS
TDO
TDI
TCK
Freescale Semiconductor
1
1
6