MC68040FE25A Freescale Semiconductor, MC68040FE25A Datasheet - Page 46

• Manufacturer Part Number: MC68040FE25A
• Description: IC MICROPROCESSOR 32BIT 184-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68040FE25A

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 184-CQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 184
• Package Type: CQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Freescale Semiconductor, Inc.
2.2.1.3 SYSTEM STACK POINTER (A7). A7 is used as a hardware stack pointer during
stacking for subroutine calls and exception handling. The register designation A7 refers to
three different uses of the register: the user stack pointer (USP) (A7) in the user
programming model and either the interrupt stack pointer (ISP) or master stack pointer
(MSP) (A7' or A7", respectively) in the supervisor programming model. When the S-bit in
the status register (SR) is clear, the USP is the active stack pointer. Explicit references to
the system stack pointer (SSP) refer to the USP while the processor is operating in the
user mode.
A subroutine call saves the program counter (PC) on the active system stack, and the
return restores it from the active system stack. Both the PC and the SR are saved on the
supervisor stack (either ISP or MSP) during the processing of exceptions and interrupts.
Thus, the execution of supervisor level code is independent of user code and condition of
the user stack. Conversely, user programs use the USP independently of supervisor stack
requirements.
2.2.1.4 PROGRAM COUNTER. The PC contains the address of the currently executing
instruction. During instruction execution and exception processing, the processor
automatically increments the contents of the PC or places a new value in the PC, as
appropriate. For some addressing modes, the PC can be used as a pointer for PC-relative
addressing.
2.2.1.5 CONDITION CODE REGISTER. The CCR consists of five bits of the SR least
significant byte. The first four bits represent a condition of the result generated by a
processor operation. The fifth bit, the extend bit (X-bit), is an operand for multiprecision
computations. The carry bit (C-bit) and the X-bit are separate in the M68000 family to
simplify programming techniques that use them.
2.2.2 Integer Unit Supervisor Programming Model
Only system programmers use the supervisor programming model (see Figure 2-4) to
implement sensitive operating system functions, I/O control, and MMU subsystems. All
accesses that affect the control features of the M68040 are in the supervisor programming
model. Thus, all application software is written to run in the user mode and migrates to the
M68040 from any M68000 platform without modification.
MOTOROLA
M68040 USER’S MANUAL
2- 5
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