TS68040VR25A Atmel, TS68040VR25A Datasheet - Page 31

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TS68040VR25A

Manufacturer Part Number
TS68040VR25A
Description
IC MPU 32BIT 25MHZ 179PGA
Manufacturer
Atmel
Datasheet

Specifications of TS68040VR25A

Processor Type
68000 32-Bit
Speed
25MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
179-PGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
TS68040
For the subset of the FPU instructions that generate exception traps, the 32-bit floating-
point instruction address register (FPIAR) is loaded with the logical address of an
instruction before the instruction is executed. This address can then be used by a float-
ing-point exception handler to locate a floating-point instruction that has caused an
exception. The move floating-point data register (FMOVE) instruction (to from the
FPCR, FPSR, or FPIAR) and the move multiple data registers (FMOVEN) instruction
cannot generate floating-point exceptions; therefore, these instructions do not modify
the FPIAR. Thus, the FMOVE and FMOVEM instructions can be used to read the
FPIAR in the trap handler without changing the previous value.
Figure 20. Programming Model
31
2116A–HIREL–09/02

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