TS68040VR33A Atmel, TS68040VR33A Datasheet - Page 21

• Manufacturer Part Number: TS68040VR33A
• Description: IC MPU 32BIT 33MHZ 179PGA
• Manufacturer: Atmel

Specifications of TS68040VR33A

• Processor Type: 68000 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 179-PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Notes:
Table 15. Input AC Timing Specifications (Figure 9 to Figure 15)
-55°C T
2116A–HIREL–09/02
Num
22a
22b
22c
22d
41a
41b
41c
41d
44a
44b
15
16
17
23
24
25
31
32
33
34
35
36
37
42
1. Output timing is specified for a valid signal measured at the pin. Large buffer timing is specified driving a 50 transmission
2. All testing to be performed using worst-case test conditions unless otherwise specified.
3. The following pins are active low: AVEC, BG, BS, BR, CDIS, CIOUT, IPEND, IPLO, IPL1, IPL2, LOCK, LOCKE, MDIS, MI,
4. Maximum operating junction temperature (T
5. Timing specifications 11, 20 and 38 for address bus output timing apply when normal bus operation is selected. Specifica-
6. Timing specifications 18 and 19 for data bus output timing apply when normal bus operation is selected. Specifications 28
C
Characteristic
Data-in Valid to BCLK (Setup)
BCLK to Data-in Invalid (Hold)
BCLK to Data-in High Impedance (Read Followed By Write)
TA Valid to BCLK (Setup)
TEA Valid to BCLK (Setup)
TBI Valid to BCLK (Setup)
BCLK to TA, TEA, TCI, TBI Invalid (Hold)
AVEC Valid to BCLK (Setup)
BCLK to AVEC Invalid (Hold)
DLE Width High
Data-in Valid to DLE (Setup)
DLE to Data-in Invalid (Hold)
BCLK to DLE Hold
DLE High to BCLK
Data-in Valid to BCLK (DLE Mode Setup)
BCLK Data-in Invalid (DLE Mode Hold)
BB Valid to BCLK (Setup)
BG Valid to BCLK (Setup)
CDIS, MDIS Valid to BCLK (Setup)
IPLn Valid to BCLK (Setup)
BCLK to BB, BG, CDIS, IPLn, MDIS Invalid (Hold)
Address Valid to BCLK (Setup)
SIZn Valid BCLK (Setup)
TCI Valid to BCLK (Setup)
line with a length characterized by a 2.5 ns one-way propagation delay, terminated through 50 to 2.5V. Large buffer output
impedance is typically 3 , resulting in incident wave switching for this environment. Small buffer timing is specified driving
an unterminated 30 transmission line with a length characterized by a 2.5 ns one-way propagation delay. Small buffer out-
put impedance is typically 30 ; the small buffer specifications include approximately 5 ns for the signal to propagate the
length of the transmission line and back.
RST0, RSTI, TA, TBI, TCI, TEA, TIP, TRST, TS and W of R/W.
tested at T
temperatures to rise and fall as necessary so as not to exceed the maximum junction temperature.
tions 26, 27 and 28 should be used when the multiplexed bus mode of operation is enabled.
and 29 should be used when the multiplexed bus mode of operation is enabled.
T
Jmax
; 4.75V V
C
= +125°. Testing is performed by setting the junction temperature T
CC
5.25V unless otherwise specified
J
) = +125°. Minimum case operating temperature (T
(1)(2)(3)(4)
Min.
10
10
16
10
11
10
12
5
4
2
5
2
8
2
8
3
5
4
7
8
4
2
8
25 MHz
J
= +125°and allowing the case and ambient
Max.
49
Min.
10
10
10
10
12
C
4
4
2
5
2
8
2
8
3
5
4
7
7
8
3
2
7
8
) = -55°. This device is not
33 MHz
TS68040
Max.
36.5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
21