TSPC603RVGU8LC Atmel, TSPC603RVGU8LC Datasheet - Page 31

• Manufacturer Part Number: TSPC603RVGU8LC
• Description: IC MPU 32BIT 8MHZ 255CBGA
• Manufacturer: Atmel

Specifications of TSPC603RVGU8LC

• Processor Type: PowerPC 603e 32-Bit RISC
• Speed: 200MHz
• Voltage: 2.5V
• Mounting Type: Surface Mount
• Package / Case: 255-CBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

5410B–HIREL–09/05
The following supervisor-level SPRs are implementation-specific to the 603R:
Figure 12-1
to the right of the SPRs indicate the number that is used in the syntax of the instruction operands
to access the register.
– The Time Base register (TB) is a 64-bit register that maintains the time of day and
– The Processor Version Register (PVR) is a 32-bit, read-only register that identifies
– Block Address Translation (BAT) arrays - The PowerPC architecture defines 16 BAT
– The DMISS and IMISS registers are read-only registers that are loaded
– The HASH1 and HASH2 registers contain the physical addresses of the primary and
– The ICMP and DCMP registers contain a duplicate of the first word in the Page Table
– The Required Physical Address (RPA) register is loaded by the processor with the
– The hardware implementation (HID0 and HID1) registers provide the means for
– The Instruction Address Breakpoint Register (IABR) is loaded with an instruction
operates interval timers. The TB consists of two 32-bit fields - Time Base Upper
(TBU) and Time Base Lower (TBL).
the version (model) and revision level of the PowerPC processor.
registers, divided into four pairs of Data BATs (DBATs) and four pairs of instruction
BATs (IBATs). See
automatically upon an instruction or data TLB miss.
secondary Page Table Entry Groups (PTEGs).
Entry (PTE) for which the table search is looking.
second word of the correct PTE during a page table search.
enabling the 603R’s checkstops and features, and allows software to read the
configuration of the PLL configuration signals.
address that is compared to instruction addresses in the dispatch queue. When an
address match occurs, an instruction address breakpoint exception is generated.
shows all the 603R registers available at the user and supervisor level. The number
Figure 12-1
for a list of the SPR numbers for the BAT arrays.
TSPC603R
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