Z85C3008PEC Zilog, Z85C3008PEC Datasheet - Page 42
![IC 8MHZ Z8500 CMOS SCC 40-DIP](/photos/6/57/65796/269-40-dip_sml.jpg)
Z85C3008PEC
Manufacturer Part Number
Z85C3008PEC
Description
IC 8MHZ Z8500 CMOS SCC 40-DIP
Manufacturer
Zilog
Datasheet
1.Z85C3008PSG.pdf
(71 pages)
Specifications of Z85C3008PEC
Processor Type
Z80
Features
Error Detection and Multiprotocol Support
Speed
8MHz
Voltage
5V
Mounting Type
Through Hole
Package / Case
40-DIP (0.620", 15.75mm)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
269-3058
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PS011705-0608
AD7–AD0
INTACK
R/W
CS0
CS1
AS
DS
Read Cycle Timing
Figure 24
and INTACK are latched by the rising edge of AS. R/W must be High to indicate a Read
cycle. CS1 must also be High for the Read cycle to occur. The data bus drivers in the SCC
are then enabled while DS is Low.
displays the Read cycle timing. The address on AD7–AD0 and the state of CS0
Address
Figure 24. Read Cycle Timing
CMOS SCC Serial Communications Controller
Data Valid
Product Specification
Functional Description
38
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