EZ80L92AZ020EC Zilog, EZ80L92AZ020EC Datasheet - Page 64

• Manufacturer Part Number: EZ80L92AZ020EC
• Description: IC WEBSERVER 20MHZ 100LQFP
• Manufacturer: Zilog

Specifications of EZ80L92AZ020EC

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 20MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3167; EZ80L92AZ020EC

PS013014-0107
Table 16. Intel
(Continued)
During Write operations with separate address and data buses, the Intel Bus Mode
employs 4 states (T1, T2, T3, and T4) as described in
Table 17. Intel
Intel Bus Mode timing is illustrated for a Read operation in
operation in
beginning of State T3, additional WAIT states (T
is driven High. The Intel Bus Mode states can be configured for 2 to 15 eZ80 system clock
cycles. In the figures, each Intel
tion.
the selected peripheral.
STATE T3
STATE T4
STATE T1
STATE T2
STATE T3
STATE T4
Figure 10
Figure
During State T3, no bus signals are altered. If the external ReadY (WAIT)
pin is driven Low at least one eZ80 system clock cycle prior to the
beginning of State T3, additional WAIT states (T
ReadY pin is driven High.
The CPU latches the Read data at the beginning of State T4. The CPU
deasserts the RD signal and completes the Intel Bus Mode cycle.
The Write cycle begins in State T1. The CPU drives the address onto the
address bus, the associated Chip Select signal is asserted, and the data is
driven onto the data bus. The CPU drives the ALE signal High at the
beginning of T1. During the middle of T1, the CPU drives ALE Low to
facilitate the latching of the address.
During State T2, the CPU asserts the WR signal. Depending on the
instruction, either the MREQ or IORQ signal is asserted.
During State T3, no bus signals are altered. If the external ReadY (WAIT)
pin is driven Low at least one eZ80 system clock cycle prior to the
beginning of State T3, additional WAIT states (T
ReadY pin is driven High.
The CPU deasserts the WR signal at the beginning of State T4. The CPU
holds the data and address buses through the end of T4. The bus cycle is
completed at the end of T4.
and
®
®
Bus Mode Read States (Separate Address and Data Buses)
Bus Mode Write States (Separate Address and Data Buses)
11. If the ReadY signal (external WAIT pin) is driven Low prior to the
Figure 11
also illustrate the assertion of one WAIT state (T
®
Bus Mode state is 2 eZ80 system clock cycles in dura-
WAIT
) are asserted until the ReadY signal
Table
Figure 10
17.
WAIT
WAIT
Chip Selects and Wait States
Product Specification
) are asserted until the
) are asserted until the
and for a Write
eZ80L92 MCU
WAIT
) by
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