NS486SXL-25 National Semiconductor, NS486SXL-25 Datasheet - Page 9

• Manufacturer Part Number: NS486SXL-25
• Description: IC NS486SXL 132PQFP
• Manufacturer: National Semiconductor

Specifications of NS486SXL-25

• Processor Type: 486SX
• Speed: 25MHz
• Voltage: 3.3V, 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Other names: *NS486SXL-25

RAS 1 0
CASH 1 0
CASL 1 0
WE
DP 1 0
Symbol
V
V
RESET
RESET
PWGOOD
Symbol
Symbol
CC
SS
2 0 Pin Description Tables
Pins
10
10
Pins
Pins
1
1
1
2
2
2
1
2
Type
Type
I
I
Type
I O
O
0
O
O
O
O
I
a
Ground to core and I O
RESET system output driver This active high signal resets or initializes system peripheral logic during
power up or during a low line voltage outage
Inverse of RESET for peripherals requiring active low reset
PoWer GOOD This active-high (Schmitt trigger) input will cause a hardware reset to the NS486SXF
whenver this input goes low This pin will typically be driven by the power supply and PWGOOD will
remain low until the power supply determines that stable and valid voltage levels have been achieved
3 3V or
Row Address Strobe On the falling edge of these active-low signals Bank 1 and Bank 0 respectively
should latch in the row address off of SA 12 1 If only one bank of DRAMs are supported RAS0 will
support that bank and RAS1 will be unused
Column Address Strobe (High Byte) These active-low signals indicate when the column access is
being made to the high byte of DRAM Bank 1 and DRAM Bank 0 respectively If only one bank of
DRAMs are supported CASH0 will support the high byte of that bank and CASH1 will be unused
Column Address Strobe (Low Byte) These active-low signals indicate when the column access is
being made to the low byte of DRAM Bank 1 and DRAM Bank 0 respectively If only one bank of
DRAMs are supported CASL0 will support the low byte of that bank and CASL1 will be unused
Write Enable Active low signal for writing the data into the DRAM bank
DRAM Data Parity DRAM data parity may be enabled or disabled if disabled these two pins will be
unused Otherwise for DRAM writes the NSC486SXF’s DRAM Controller will generate odd parity and
drive the odd parity onto these two pins For DRAM reads the NS486SXF’s DRAM Controller will read
the values driven on these two pins and check it for odd parity in association with the appropriate data
byte
a
5V power to core and I O
(Continued)
TABLE 2-3 DRAM Control Pins
TABLE 2-5 Reset Logic Pins
TABLE 2-4 Power Pins
9
Function
Function
Function