MC68306FC16B Freescale Semiconductor, MC68306FC16B Datasheet
MC68306FC16B
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MC68306FC16B Summary of contents
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... Freescale Semiconductor, Inc. Integrated EC000 Processor Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. " ...
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... Freescale Semiconductor, Inc. The complete documentation package for the MC68306 consists of the MC68306UM/AD, MC68306 EC000 Integrated Processor User’s Manual , M68000PM/AD, MC68000 Family Programmer’s Reference Manual, and the MC68306P/D, MC68306 EC000 Integrated Processor Product Brief . The MC68306 EC000 Integrated Processor User’s Manual describes the programming, capabilities, registers, and operation of the MC68306 ...
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... Freescale Semiconductor, Inc. UNITED STATES ALABAMA, Huntsville ARIZONA, Tempe CALIFORNIA, Agoura Hills CALIFORNIA, Los Angeles CALIFORNIA, Irvine CALIFORNIA, Rosevllle CALIFORNIA, San Diego CALIFORNIA, Sunnyvale COLORADO , Colorado Springs COLORADO , Denver CONNECTICUT, Wallingford FLORIDA , Maitland FLORIDA , Pompano Beach/ Fort Lauderdale FLORIDA , Clearwater GEORGlA , Atlanta ...
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... Freescale Semiconductor, Inc. TABLE OF CONTENTS Paragraph Number 1.1 MC68EC000 Core processor.................................................................................. 1-2 1.2 On-Chip Peripherals ............................................................................................... 1-3 1.2.1 Serial Module ....................................................................................................... 1-3 1.2.2 DRAM Controller .................................................................................................. 1-4 1.2.3 Chip Selects......................................................................................................... 1-4 1.2.4 Parallel Ports........................................................................................................ 1-4 1.2.5 Interrupt Controller ............................................................................................... 1-4 1.2.6 Clock .................................................................................................................... 1-5 1.2.7 Bus Timeout Monitor ............................................................................................ 1-5 1 ...
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... Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Number 2.3 DRAM Controller Signals........................................................................................ 2-9 2.3.1 Column Address Strobe (CAS1– CAS0 )............................................................... 2-9 2.3.2 Row Address Strobe (RAS1 –RAS0) .................................................................... 2-9 2.3.3 DRAM Write Signal (DRAMW) ............................................................................. 2-9 2.4 Interrupt Control and Parallel Port Signals ............................................................. 2-9 2.4.1 Interrupt Request (IRQ7– ...
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... Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Number 3.2 Bus Arbitration ........................................................................................................ 3-12 3.2.1 Requesting the Bus ............................................................................................. 3-15 3.2.2 Receiving the Bus Grant ...................................................................................... 3-16 3.2.3 Acknowledgment of Mastership (3-Wire Bus Arbitration Only) ............................ 3-16 3.3 Bus Arbitration Control ............................................................................................ 3-16 3.4 Bus Error and Halt Operation ................................................................................. 3-24 3 ...
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... Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Number 5.1 MC68306 Address Space ....................................................................................... 5-1 5.2 Register Description ............................................................................................... 5-3 5.2.1 System Register .................................................................................................. 5-3 5.2.2 Timer Vector Register .......................................................................................... 5-4 5.2.3 Bus Timeout Period Register............................................................................... 5-4 5.2.4 Interrupt Registers ............................................................................................... 5-5 5.2.4.1 Interrupt Control Register ................................................................................. 5-5 5 ...
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... Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Number 6.2.8.1 RTSB ................................................................................................................ 6-6 6.2.8.2 OP1................................................................................................................... 6-6 6.2.9 Channel A Clear-To-Send (CTSA/IP0) ................................................................ 6-6 6.2.9.1 CTSA ................................................................................................................ 6-6 6.2.9.2 IP0 .................................................................................................................... 6-6 6.2.10 Channel B Clear-To-Send (CTSB/IP1) .............................................................. 6-6 6.2.10.1 CTSB .............................................................................................................. 6-6 6.2.10.2 IP1 .................................................................................................................. 6-6 6.3 Operation ................................................................................................................ 6-7 6.3.1 Baud Rate Generator........................................................................................... 6-7 6 ...
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... Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Number 6.4.1.15 Counter/Timer Lower Pimer Register (CTLR) ................................................ 6-34 6.4.1.16 Interrupt Vector Register (DUIVR) .................................................................. 6-34 6.4.1.17 Input Port Register .......................................................................................... 6-34 6.4.1.18 Output Port Control Register (DUOPCR) ....................................................... 6-35 6.4.1.19 Output Port Data Register (DUOP) ................................................................ 6-35 6.4.1.20 Start Counter Command Register .................................................................. 6-36 6 ...
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... Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Number 8.14 AC Electrical Characteristics—Interrupt Reset ..................................................... 8-16 8.15 AC Electrical Characteristics—Transmitter Timing ............................................... 8-17 8.16 AC Electrical Characteristics—Receiver Timing ................................................... 8-18 8.17 IEEE 1149.1 Electrical Characteristics ................................................................. 8-19 Ordering Information and Mechanical Data 9.1 Standard Ordering Information ............................................................................... 9-1 9 ...
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... Freescale Semiconductor, Inc. LIST OF ILLUSTRATIONS Figure Number Figure 1-1. MC68306 Simplified Block Diagram....................................................... 1-1 Figure 2-1. MC68306 Detailed Block Diagram ......................................................... 2-2 Figure 3-1. Word Read Cycle Flowchart .................................................................. 3-2 Figure 3-2. Byte Read Cycle Flowchart .................................................................... 3-2 Figure 3-3. Read and Write Cycle Timing Diagram .................................................. 3-3 Figure 3-4 ...
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... Freescale Semiconductor, Inc. LIST OF ILLUSTRATIONS (Continued) Figure Number Figure 4-1. Programmer's Model .............................................................................. 4-2 Figure 4-2. Status Register ....................................................................................... 4-3 Figure 4-3. General Exception Processing Flowchart .............................................. 4-13 Figure 4-4. General Form of Exception Stack Frame ............................................... 4-14 Figure 4-5. Exception Vector Format ........................................................................ 4-15 Figure 4-6. Address Translated from 8-Bit Vector Number ...................................... 4-15 Figure 4-7 ...
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... Freescale Semiconductor, Inc. LIST OF ILLUSTRATIONS (Continued) Figure Number Figure 8-11. DRAM Timing – 1-Wait, Test and Set .................................................. 8-15 Figure 8-12. Clock Timing......................................................................................... 8-16 Figure 8-13. Port Timing ........................................................................................... 8-16 Figure 8-14. Interrupt Reset Timing .......................................................................... 8-17 Figure 8-15. Transmit Timing ................................................................................... 8-17 Figure 8-16. Receive Timing .................................................................................... 8-18 Figure 8-17 ...
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... Freescale Semiconductor, Inc. Table Number Table 2-1. Bus Signal Summary ............................................................................... 2-3 Table 2-2. Chip Select Signal Summary ................................................................... 2-3 Table 2-3. DRAM Controller Signal Summary .......................................................... 2-3 Table 2-4. Interrupt and Parallel Port Signal Summary ............................................ 2-4 Table 2-5. Clock and Mode Control Signal Summary............................................... 2-4 Table 2-6 ...
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... Freescale Semiconductor, Inc. LIST OF TABLES (Continued) Table Number Table 7-1. Boundary Scan Control Bits .................................................................... 7-4 Table 7-2. Boundary Scan Bit Definitions ................................................................. 7-5 Table 7-3. Instructions .............................................................................................. 7-10 xvi For More Information On This Product, Title MC68306 USER'S MANUAL Go to: www.freescale.com Page Number MOTOROLA ...
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... Freescale Semiconductor, Inc. SECTION 1 INTRODUCTION The MC68306 is an integrated processor containing an MC68EC000 processor and elements common to many MC68000- and MC68EC000-based systems. Designers of virtually any application requiring MC68000-class performance will find that the MC68306 reduces design time by providing valuable system elements integrated in one chip. The combination of peripherals offered in the MC68306 can be found in a diverse range of microprocessor-based systems, including embedded control and general computing ...
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... Freescale Semiconductor, Inc. The primary features of the MC68306 are as follows: • Functional Integration on a Single Piece of Silicon • EC000 Core—Identical to MC68EC000 Microprocessor — Complete Code Compatibility with MC68000 and MC68EC000 — High Performance—2.4 MIPS — Extended Internal Address Range – Gbyte • ...
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... Freescale Semiconductor, Inc. these instructions, including predecrement and postincrement, which allow simple stack and queue maintenance and scaled indexing for efficient table accesses. Data types and addressing modes are supported orthogonally by all data operations and with all appropriate addressing modes. Position-independent code is easily written. ...
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... Freescale Semiconductor, Inc. between the processor and DRAM. The MC68306 contains a full DRAM controller, greatly reducing design time and complexity. The DRAM controller provides row address strobe (RAS) and column address strobe (CAS) signals for two separate banks of DRAMs. Each bank can include devices; ...
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... Freescale Semiconductor, Inc. external 16.67-MHz oscillator can be used, with a tight skew between the input clock signal and the bus clock on the CLKOUT pin. 1.2.7 Bus Timeout Monitor A bus timeout monitor is provided to automatically terminate and report as erroneous any bus cycle that is not normally terminated after a pre-programmed length of time. The user can program this timeout period 4096 clocks ...
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... Freescale Semiconductor, Inc. SECTION 2 SIGNAL DESCRIPTION This section contains a brief description of the input and output signals, with reference (if applicable) to other sections which give greater detail on its use. Figure 2-1 provides a detailed diagram showing the integrated peripherals and signals, and Tables 2-1–2-7 provides a quick reference for determining a signal's name, mnemonic, its use as an input or output, active state, and type identification ...
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... Freescale Semiconductor, Inc. DRAMW RAS1 DRAM RAS0 CONTROLLER CAS1 CAS0 EXTAL CLOCK XTAL CLKOUT MODE AMODE CONTROLLER JTAG PORT TRST IRQ7 IRQ4 INTERRUPT IRQ1 CONTROLLER IACK7 IACK4 IACK1 IRQ6/PB7 IRQ5/PB6 IRQ3/PB5 IRQ2/PB4 PORT B IACK6/PB3 IACK5/PB2 IACK3/PB1 IACK2/PB0 Figure 2-1. MC68306 Detailed Block Diagram ...
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... Freescale Semiconductor, Inc. Table 2-1. Bus Signal Summary Signal Name Address Signals Address Strobe Bus Error Bus Grant Bus Grant Acknowledge Bus Request Data Bus Data Transfer Acknowledge DRAM Multiplexed Address14–0 DRAMA14–DRAMA0 Function Codes Halt Lower Data Strobe Upper Data Strobe ...
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... Freescale Semiconductor, Inc. Table 2-4. Interrupt and Parallel Port Signal Summary Signal Name Interrupt Request Level Interrupt Request Level 6/Port B 7 Interrupt Request Level 5/Port B 6 Interrupt Request Level 3/Port B 5 Interrupt Request Level 2/Port B 4 Interrupt Acknowledge IACK7, IACK4, IACK1 ...
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... Freescale Semiconductor, Inc. Table 2-6. Serial Module Signal Summary Signal Name Channel A Receiver Serial Data Channel A Transmitter Serial Data Channel B Receiver Serial Data Channel B Transmitter Serial Data Channel A Clear-to-Send Channel A Request-to-Send Channel B Clear-to-Send Channel B Request-to-Send Crystal Output Crystal Input or External Clock ...
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... Freescale Semiconductor, Inc. are driven to logic high. A23–A20 are only available in address mode (AMODE=0). A15– A1 are multiplexed with DRAM address. AS 2.1.2 Address Strobe ( Assertion of this three-state signal indicates that the information on the address bus is a valid address. BERR 2.1.3 Bus Error ( ...
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... Freescale Semiconductor, Inc. BGACK can be negated (pulled high), and the MC68306 will operate in a two-wire bus arbitration system. 2.1.7 Data Bus (D15–D0) This bi-directional, three-state bus is the general-purpose data path bits wide and can transfer and accept data of either word or byte length. During an interrupt acknowledge cycle, an external device can supply the interrupt vector number on data lines D7– ...
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... Freescale Semiconductor, Inc. additional information about the interaction between HALT and RESET , refer to 3.5 Reset Operation and for more information on HALT and BERR , refer to 3.4 Bus Error and Halt Operation. Processor assertion of HALT indicates a double bus fault condition. This condition is unrecoverable; the MC68306 must be externally reset to resume operation. ...
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... Freescale Semiconductor, Inc. 2.1.15 Lower-Byte Write ( This signal is a combination of R/W low and LDS low for writing the lower-byte of a 16-bit port. This signal simplifies memory system design by explicitly signalling that data is valid on the lower portion of the data bus on a write operation also decoded for external bus masters ...
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... Freescale Semiconductor, Inc. 2.4.1 Interrupt Request (IRQ7–IRQ1) Three input signals (IRQ7, IRQ4, IRQ1) notify the core processor of an interrupt request. Four additional interrupt request lines (IRQ6, IRQ5, IRQ3, and IRQ2) are shared with parallel port B pins and may be individually programmed as interrupts. ...
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... Freescale Semiconductor, Inc. 2.6.1 Channel A Receiver Serial-Data Input (RxDA) This signal is the receiver serial-data input for channel A. The least-significant bit is received first. Data on this pin is sampled on the rising edge of the programmed clock source. 2.6.2 Channel A Transmitter Serial-Data Output (TxDA) This signal is the transmitter serial-data output for channel A. The least-significant bit is transmitted first ...
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... Freescale Semiconductor, Inc. 2.6.9 Crystal Oscillator (X1/CLK, X2) These two pins are the connections for an external crystal to the internal oscillator circuit external oscillator is used, it should be connected to X1/CLK, with X2 left floating, and must drive CMOS levels. A crystal or clock input must be supplied at all times. ...
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... Freescale Semiconductor, Inc. SECTION 3 68000 BUS OPERATION DESCRIPTION This section describes control signal and bus operation during data transfer operations, bus arbitration, bus error and halt conditions, and reset operation. The terms assertion and negation are used extensively in this manual to avoid confusion when describing a mixture of " ...
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... Freescale Semiconductor, Inc. The word read cycle flowchart is shown in Figure 3-1. The byte read cycle flowchart is shown in Figure 3-2. The read and write cycle timing is shown in Figure 3-3. Figure 3-4 shows the word and byte read cycle timing diagram. BUS MASTER ...
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... Freescale Semiconductor, Inc CLK FC2–FC0 A31–A1 AS UDS LDS R/W DTACK D15–D8 D7–D0 READ Figure 3-3. Read and Write Cycle Timing Diagram CLK FC2–FC0 A31– UDS LDS R/W DTACK D15–D8 D7–D0 READ *Internal Signal Only Figure 3-4. Word and Byte Read Cycle Timing Diagram ...
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... Freescale Semiconductor, Inc. A bus cycle consists of eight states. The various signals are asserted during specific states of a read cycle as follows: STATE 0 The read cycle starts in state 0 (S0). The processor places valid function codes on FC0–FC2, a valid address on the bus, and drives R/W high to identify a read cycle ...
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... Freescale Semiconductor, Inc. strobe. When the A0 bit equals zero, UDS is asserted; when the A0 bit equals one, LDS is asserted. The word write cycle flowchart is shown in Figure 3-5. The byte write cycle flowchart is shown in Figure 3-6. The word and byte write cycle timing is shown in Figure 3-7. ...
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... Freescale Semiconductor, Inc. BUS MASTER ADDRESS THE DEVICE 1) PLACE FUNCTION CODE ON FC2–FC0 2) PLACE ADDRESS ON ADDRESS BUS 3) ASSERT ADDRESS STROBE (AS) 4) SET R/W TO WRITE 5) PLACE DATA ON D0–D7 OR D15–D8 (ACCORDING TO INTERNAL A0) 6) ASSERT UPPER DATA STROBE (UDS) OR LOWER DATA STROBE (LDS) ...
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... Freescale Semiconductor, Inc. The descriptions of the eight states of a write cycle are as follows: STATE 0 The write cycle starts in S0. The processor places valid function codes on FC2–FC0, a valid address on the address bus, and drives R/W high (if a preceding write cycle has left R/W low). ...
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... Freescale Semiconductor, Inc. that uses the read-modify-write cycle) only operates on bytes. Thus, all read-modify-write cycles are byte operations. The read-modify-write flowchart is shown in Figure 3-8 and the timing diagram is shown in Figure 3-9. BUS MASTER ADDRESS THE DEVICE 1) SET R/W TO READ 2) PLACE FUNCTION CODE ON FC2–FC0 ...
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... Freescale Semiconductor, Inc CLK A31–A1 AS UDS OR LDS R/W DTACK D15–D8 OR D7–D0 FC2–FC0 Figure 3-9. Read-Modify-Write Cycle Timing Diagram The descriptions of the read-modify-write cycle states are as follows: STATE 0 The read cycle starts in S0. The processor places valid function codes on FC2– ...
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... Freescale Semiconductor, Inc. STATE 12 The write portion of the cycle starts in S12. The valid function codes on FC2–FC0, the address bus lines, AS, and R/W remain unaltered. STATE 13 During S13, no bus signals are altered. STATE 14 On the rising edge of S14, the processor drives R/W low. ...
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... Freescale Semiconductor, Inc. STATE 17 During S17, no bus signals are altered. STATE 18 During S18, no bus signals are altered. STATE 19 During S19, no bus signals are altered. STATE 20 During S20. no bus signals are altered. STATE 21 The processor negates AS and UDS /LDS. 3.1.4 CPU Space Cycle A CPU space cycle, indicated when the function codes are all high special processor cycle ...
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... Freescale Semiconductor, Inc. IPL2–IPL0 VALID INTERNALLY IPL2–IPL0 SAMPLED IPL2–IPL0 TRANSITION CLK FC2–FC0 A23–A4 A3– UDS LDS IACK R/W DTACK D15–D8 D7–D0 IPL2–IPL0 LAST BUS CYCLE OF INSTRUCTION (READ OR WRITE) * Although a vector number is one byte, both data strobes are asserted due to the microcode used for exception processing. The processor does not recognize anything on data lines D8 through D15 at this time ...
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... Freescale Semiconductor, Inc. There are two ways to arbitrate the bus, 3-wire and 2-wire bus arbitration. The EC000 core can do either 2-wire or 3-wire bus arbitration. Figures 3-12 and 3-14 show 3-wire bus arbitration and Figures 3-13 and 5-15 show 2-wire bus arbitration. BGACK must be pulled high for 2-wire bus arbitration ...
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... Freescale Semiconductor, Inc. PROCESSOR GRANT BUS ARBITRATION 1) ASSERT BUS GRANT (BG) ACKNOWLEDGE RELEASE OF BUS MASTERSHIP 1) NEGATE BUS GRANT (BG) REARBITRATE OR RESUME PROCESSOR OPERATION Figure 3-13. Two-Wire Bus Arbitration Cycle Flowchart 3-14 For More Information On This Product, 1) ASSERT BUS REQUEST (BR) OPERATE AS BUS MASTER 1) EXTERNAL ARBITRATION DETER- ...
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... Freescale Semiconductor, Inc. CLK FC2–FC0 A31–A1 AS LDS/ UDS R/W DTACK D15– BGACK PROCESSOR DMA DEVICE Figure 3-14. Three-Wire Bus Arbitration Timing Diagram CLK FC2–FC0 A19– R/W DTACK D7– PROCESSOR DMA DEVICE Figure 3-15. Two-Wire Bus Arbitration Timing Diagram ...
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... Freescale Semiconductor, Inc. The timing diagram in Figure 3-14 shows that the bus request is negated at the time that an acknowledge is asserted. This type of operation applies to a system consisting of a processor and one other device capable of becoming bus master. In systems having several devices that can be bus masters, bus request lines from these devices can be wire-ORed at the processor, and more than one bus request signal could occur ...
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... Freescale Semiconductor, Inc. The bus request from the granted device should be negated after BGACK is asserted. If another bus request is pending reasserted within a few clocks, as described in 3.3 Bus Arbitration Control. The processor does not perform any external bus cycles before reasserting BG . 3.3 BUS ARBITRATION CONTROL All asynchronous bus arbitration signals to the processor are synchronized before being used internally ...
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... Freescale Semiconductor, Inc. When a bus request is made after the MPU has begun a bus cycle and before AS has been asserted (S0), the special sequence shown in Figure 3-20 applies. Instead of being asserted on the next rising edge of clock delayed until the second rising edge following its internal assertion. ...
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... Freescale Semiconductor, Inc. Figures 3-18, 3-19, and 3-20 apply to processors using 3-wire bus arbitration. Figures 3-21, 3-22, and 3-23 apply to processors using 2-wire bus arbitration. BUS THREE-STATED BG ASSERTED BR VALID INTERNAL BR SAMPLED BR ASSERTED CLK BGACK FC2–FC0 A31–A1 AS UDS LDS R/W DTACK D15– ...
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... Freescale Semiconductor, Inc. BUS RELEASED FROM THREE STATE AND PROCESSOR STARTS NEXT BUS CYCLE BGACK NEGATED BG ASSERTED AND BUS THREE STATED BR VALID INTERNAL BR SAMPLED BR ASSERTED CLK BGACK FC2–FC0 A31–A1 AS UDS LDS R/W DTACK D15–D0 PROCESSOR Figure 3-19. Three-Wire Bus Arbitration Timing Diagram—Bus Inactive ...
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... Freescale Semiconductor, Inc. BUS THREE-STATED BG ASSERTED BR VALID INTERNAL BR SAMPLED BR ASSERTED CLK BGACK FC2–FC0 A31–A1 AS UDS LDS R/W DTACK D15–D0 PROCESSOR Figure 3-20. Three-Wire Bus Arbitration Timing Diagram—Special Case MOTOROLA For More Information On This Product, BUS RELEASED FROM THREE STATE AND ...
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... Freescale Semiconductor, Inc. BUS THREE-STATED BG ASSERTED BR VALID INTERNAL BR SAMPLED BR ASSERTED CLK BGACK FC2–FC0 A31–A1 AS UDS LDS R/W DTACK D15–D0 PROCESSOR Figure 3-21. Two-Wire Bus Arbitration Timing Diagram—Processor Active 3-22 For More Information On This Product, BUS RELEASED FROM THREE STATE AND ...
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... Freescale Semiconductor, Inc. BUS RELEASED FROM THREE STATE AND PROCESSOR STARTS NEXT BUS CYCLE BR NEGATED BG ASSERTED AND BUS THREE STATED BR VALID INTERNAL BR SAMPLED BR ASSERTED CLK BGACK FC2–FC0 A31–A1 AS UDS LDS R/W DTACK D15–D0 PROCESSOR Figure 3-22. Two-Wire Bus Arbitration Timing Diagram—Bus Inactive ...
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... Freescale Semiconductor, Inc. BUS THREE-STATED BG ASSERTED BR VALID INTERNAL BR SAMPLED BR ASSERTED CLK BGACK FC2–FC0 A31–A1 AS UDS LDS R/W DTACK D15–D0 PROCESSOR Figure 3-23. Two-Wire Bus Arbitration Timing Diagram—Special Case 3.4 BUS ERROR AND HALT OPERATION In a bus architecture that requires a handshake from an external device, such as the asynchronous bus used in the M68000 Family, the handshake may not always occur ...
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... Freescale Semiconductor, Inc. (BERR alone). As long as BERR remains asserted, the data bus is in the high-impedance state. Figure 3-24 shows the timing for the normal bus error CLK FC2–FC0 A31–A1 AS LDS/UDS R/W DTACK D15–D0 BERR HALT INITIATE RESPONSE READ FAILURE Figure 3-24 ...
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... Freescale Semiconductor, Inc CLK FC2-FC0 A23–A1 AS LDS/UDS R/W DTACK D15–D0 BERR HALT READ Figure 3-25. Retry Bus Cycle Timing Diagram The processor terminates the bus cycle, and remains in this state until HALT is negated. Then the processor retries the preceding cycle using the same function codes, address, and data (for a write operation) ...
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... Freescale Semiconductor, Inc CLK FC2–FC0 A31–A1 AS LDS/UDS R/W DTACK D15–D0 HALT READ Figure 3-26. Halt Operation Timing Diagram The single-step mode is derived from correctly timed transitions of HALT. HALT is negated to allow the processor to begin a bus cycle, then asserted to enter the halt mode when the cycle completes ...
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... Freescale Semiconductor, Inc. After the processor is reset, it reads the reset vector table entry (address $00000) and loads the contents into the supervisor stack pointer (SSP). Next, the processor loads the contents of address $00004 (vector table entry 1) into the program counter. Then the processor initializes the interrupt level in the status register to a value of seven ...
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... Freescale Semiconductor, Inc. The possible bus cycle terminations can be summarized as follows (case numbers refer to Table 3-1). Normal Termination: DTACK is asserted. BERR and HALT remain negated (case 1). Halt Termination: HALT is asserted coincident with or preceding DTACK, and BERR remains negated (case 2). Bus Error Termination: BERR is asserted in lieu of, coincident with, or preceding DTACK (case 3) ...
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... Freescale Semiconductor, Inc. The negation of BERR and HALT under several conditions is shown in Table 3-2. (DTACK is assumed to be negated normally in all cases; for reliable operation, both DTACK and BERR should be negated when address strobe is negated). EXAMPLE A: A system uses a watchdog timer to terminate accesses to unused address space. The timer asserts BERR after timeout (case 3) ...
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... Freescale Semiconductor, Inc. ADDR AS R/W UDS/LDS DATA DTACK Figure 3-28 Fully Asynchronous Read Cycle ADDR AS R/W UDS/LDS DATA DTACK Figure 3-29. Fully Asynchronous Write Cycle In the asynchronous mode, the accessed device operates independently of the frequency and phase of the system clock. For example, the MC68681 dual universal asynchronous receiver/transmitter (DUART) does not require any clock-related information from the bus master during a bus transfer ...
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... Freescale Semiconductor, Inc pseudo-asynchronous system, timing specifications allow DTACK to be asserted for a read cycle before the data from a slave device is valid. The length of time that DTACK may precede data is specified as parameter #31. This parameter must be met to ensure the validity of the data latched into the processor. No maximum time is specified from the assertion the assertion of DTACK ...
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... Freescale Semiconductor, Inc. ADDR AS R/W UDS/LDS DATA DTACK Figure 3-31. Pseudo-Asynchronous Write Cycle 3.8 SYNCHRONOUS OPERATION In some systems, external devices use the system clock to generate DTACK and other asynchronous input signals. This synchronous operation provides a closely coupled design with maximum performance, appropriate for frequently accessed parts of the system ...
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... Freescale Semiconductor, Inc. STATE 1 Entering S1, a low period of the clock, the address of the accessed device is driven externally with an assertion delay defined by parameter #6. STATE 2 On the rising edge of S2, a high period of the clock asserted. During a read cycle, UDS and/or LDS is also asserted at this time. Parameter #9 defines the assertion delay for these signals ...
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... Freescale Semiconductor, Inc. On the rising edge of the clock, at the end of S7 (which may be the start of S0 for the next bus cycle), the processor places the address bus in the high-impedance state. During a write cycle, the processor also places the data bus in the high-impedance state and drives R/W high. External logic circuitry should respond to the negation of the AS and UDS /LDS by negating DTACK and/or BERR ...
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... Freescale Semiconductor, Inc CLOCK 6 ADDR AS UDS/LDS 18 R/W DTACK DATA Figure 3-33. Synchronous Write Cycle A key consideration when designing in a synchronous environment is the timing for the assertion of DTACK and BERR by an external device. To properly use external inputs, the processor must synchronize these signals to the internal clock. The processor must ...
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... Freescale Semiconductor, Inc. SECTION 4 EC000 CORE PROCESSOR The EC000 core has a 16-bit data bus and 32-bit address bus while the full architecture provides for 32-bit address and data register operations. 4.1 FEATURES The following resources are available to the EC000 core: • 8 32-Bit Address Registers • ...
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... Freescale Semiconductor, Inc. 4.3 PROGRAMMING MODEL The EC000 core executes instructions in one of two modes—user mode or supervisor mode. The user mode provides the execution environment for the majority of application programs. The supervisor mode, which allows some additional instructions and privileges, is used by the operating system and other system software. ...
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... Freescale Semiconductor, Inc. The status register, illustrated in Figure 4-2, contains the interrupt mask (eight levels available) and the following condition codes: overflow (V), zero (Z), negative (N), carry (C), and extend (X). Additional status bits indicate that the processor is in the trace (T) mode and/or in the supervisor (S) state. ...
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... Freescale Semiconductor, Inc. 4.3.2 Addressing Capabilities Summary The EC000 core supports the basic addressing modes of the M68000 family. The register indirect addressing modes support postincrement, predecrement, offset, and indexing, which are particularly useful for handling data structures common to sophisticated applications and high-level languages. The program counter indirect mode also has indexing and offset capabilities ...
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... Freescale Semiconductor, Inc. 4.3.3 Notation Conventions Table 4-3 lists the notation conventions used in this manual unless otherwise specified. Table 4-3. Notation Conventions + Arithmetic addition or postincrement indicator. – Arithmetic subtraction or predecrement indicator. Arithmetic multiplication. Arithmetic division or conjunction symbol. ~ Invert; operand is logically complemented. ...
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... Freescale Semiconductor, Inc. Table 4-3. Notation Conventions (Continued) <fmt> Operand Data Format: Byte (B), Word (W), Long (L), or Packed (P Specifies a signed integer data type (twos complement) of byte, word, or long word twos complement signed integer (–64 to +17) specifying a number’s format to be stored in the packed decimal format. ...
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... Freescale Semiconductor, Inc. Table 4-3. Notation Conventions (Concluded) * General Case. C Carry Bit in CCR cc Condition Codes from CCR FC Function Code N Negative Bit in CCR U Undefined, Reserved for Motorola Use. V Overflow Bit in CCR X Extend Bit in CCR Z Zero Bit in CCR — Not Affected or Applicable. SP Active Stack Pointer ...
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... Freescale Semiconductor, Inc. Table 4-4. EC000 Core Instruction Set Summary Opcode ABCD BCD Source + BCD Destination + X ˘ Destination ADD Source + Destination ˘ Destination ADDA Source + Destination ˘ Destination ADDI Immediate Data + Destination ˘ Destination ADDQ Immediate Data + Destination ˘ Destination ADDX Source + Destination + X ˘ ...
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... Freescale Semiconductor, Inc. Table 4-4. EC000 Core Instruction Set Summary (Continued) Opcode CMPM Destination – Source ˘ cc DBcc If condition false then (Dn–1 ˘ Dn –1 then ˘ PC) DIVS Destination Source ˘ Destination DIVU Destination Source ˘ Destination EOR Source Destination ˘ Destination ...
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... Freescale Semiconductor, Inc. Table 4-4. EC000 Core Instruction Set Summary (Continued) Opcode MOVEA Source ˘ Destination MOVEM Registers ˘ Destination Source ˘ Registers MOVEP Source ˘ Destination MOVEQ Immediate Data ˘ Destination MULS Source Destination ˘ Destination MULU Source Destination ˘ Destination NBCD 0 – ...
Page 79
... Freescale Semiconductor, Inc. Table 4-4. EC000 Core Instruction Set Summary (Concluded) Opcode SBCD Destination 10 – Source 10 – X ˘ Destination Scc If condition true then 1s ˘ Destination else 0s ˘ Destination STOP If supervisor state then Immediate Data ˘ SR; STOP else TRAP SUB Destination – Source ˘ Destination SUBA Destination – ...
Page 80
... Freescale Semiconductor, Inc. 4.5 EXCEPTION PROCESSING This section describes the processing for each type of exception, exception priorities, the return from an exception, and bus fault recovery. This section also describes the formats of the exception stack frames. Exception processing is the activity performed by the processor in preparing to execute a special routine for any condition that causes an exception ...
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... Freescale Semiconductor, Inc. SAVE INTERNAL COPY OF SR (SEE NOTE) FETCH VECTOR NUMBER OTHERWISE SAVE CONTENTS TO STACK FRAME (SEE NOTE) OTHERWISE EXECUTE EXCEPTION HANDLER OTHERWISE BEGIN INSTRUCTION EXECUTION NOTE: These blocks vary for reset and interrupt exceptions. Figure 4-3. General Exception Processing Flowchart ...
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... Freescale Semiconductor, Inc. The third step is to save the current processor contents for all exceptions other than reset exception, which does not stack information. The processor creates an exception stack frame on the active supervisor stack and fills it with information appropriate for the type of exception ...
Page 83
... Freescale Semiconductor, Inc. EVEN BYTE (A0=0) WORD 0 WORD 1 Figure 4-5. Exception Vector Format A31 ALL ZEROES Figure 4-6. Address Translated from 8-Bit Vector Number The actual address on the address bus is truncated to the number of address bits available on the bus of the particular implementation of the M68000 architecture. In the EC000 core, this is 24 address bits ...
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... Freescale Semiconductor, Inc. Table 4-5. Exception Vector Assignments Vector Vector Offset Number(s) (Hex) 0 000 1 004 2 008 3 00C 4 010 5 014 6 018 7 01C 8 020 9 024 10 028 11 02C 12 1 030 13 1 034 14 038 15 03C 16–23 1 040–05C 24 060 25 064 26 068 27 06C 28 070 29 074 30 078 ...
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... Freescale Semiconductor, Inc. 4.6.1 Reset Exception The reset exception corresponds to the highest exception level. The processing of the reset exception is performed for system initiation and recovery from catastrophic failure. Any processing in progress at the time of the reset is aborted and cannot be recovered. The processor is forced into the supervisor state, and the trace state is forced off. The interrupt priority mask is set at level 7 ...
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... Freescale Semiconductor, Inc. the interrupt is considered spurious, and the generated vector number references the spurious interrupt vector. The processor then proceeds with the usual exception processing. The saved value of the program counter is the address of the instruction that would have been executed had the interrupt not been taken. The appropriate interrupt vector is fetched and loaded into the program counter, and normal instruction execution commences in the interrupt handling routine ...
Page 87
... Freescale Semiconductor, Inc. instructions using the opcodes of any of the illegal instructions. Three bit patterns always force an illegal instruction trap on all M68000 family-compatible microprocessors. The patterns are: $4AFA, $4AFB, and $4AFC. Two of the patterns, $4AFA and $4AFB, are reserved for Motorola system products. The third pattern, $4AFC, is reserved for customer use (as the take illegal instruction trap (ILLEGAL) instruction). Word patterns with bits 15– ...
Page 88
... Freescale Semiconductor, Inc. instruction is not executed because an interrupt is taken or because the instruction is illegal or privileged, the trace exception does not occur. The trace exception also does not occur if the instruction is aborted by a reset, bus error, or address error exception. If the instruction is executed and an interrupt is pending on completion, the trace exception is processed before the interrupt exception ...
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... Freescale Semiconductor, Inc. error, it does allow software diagnosis. Finally, the processor commences instruction processing at the address in the vector the responsibility of the error handler routine to clean up the stack and determine where to continue execution bus error occurs during the exception processing for a bus error, an address error reset, the processor halts and all processing ceases ...
Page 90
... Freescale Semiconductor, Inc. Table 4-6. Exception Grouping and Priority Group Exception 0 Reset, Address Error, and Bus Error 1 Trace, Interrupt, Illegal, and Privilege 2 TRAP, TRAPV, CHK, and DIV The priority relationship between two exceptions determines which is taken, or taken first, if the conditions for both arise simultaneously. Therefore bus error occurs during a TRAP instruction, the bus error takes precedence, and the TRAP instruction processing is aborted ...
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... Freescale Semiconductor, Inc. SECTION 5 SYSTEM OPERATION This section contains detailed descriptions and programming information for the system functions and registers outside the EC000 core in the MC68306. None of the MC68306 internal resources are accessible by an external bus master. The following address map and operation descriptions apply only to accesses by the internal EC000 core ...
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... Freescale Semiconductor, Inc. Table 5-1. MC68306 Memory Map FC A(31–0) D(15–8) (EVEN ADDRESS) 5 FFFFFFFE/F 5 FFFFFFFC/D 5 FFFFFFFA 5 FFFFFFF8 5 FFFFFFF6 5 FFFFFFF4/5 5 FFFFFFF2/3 5 FFFFFFF0/1 5 FFFFFFEF– FFFFFFE8 5 FFFFFFE6 FFFFFFE4 5 FFFFFFE2 FFFFFFE0 5 FFFFFFDE FFFFFFDC 5 FFFFFFDA FFFFFFD8 5 FFFFFFD6 FFFFFFD4 5 FFFFFFD2 FFFFFFD0 5 FFFFFFCE FFFFFFCC 5 FFFFFFCA FFFFFFC8 ...
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... Freescale Semiconductor, Inc. 5.2 REGISTER DESCRIPTION The following paragraphs describe the registers in the MC68306. The address of the register is listed above the register. The numbers in the first row are the bit positions of each bit in the register. The second row is the bit mnemonic. The reset value for each bit is listed beneath the bit mnemonic ...
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... Freescale Semiconductor, Inc. DUIPL2–0—DUART Interrupt Priority Level This bit selects the interrupt priority level for the serial module. 000 = Reserved 001 = Interrupt priority level 1 010 = Interrupt priority level 2 011 = Interrupt priority level 3 100 = Interrupt priority level 4 101 = Interrupt priority level 5 ...
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... Freescale Semiconductor, Inc. Where: EXTAL is the crystal period in nanoseconds and period is in nanoseconds. 5.2.4 Interrupt Registers Up to seven prioritized external interrupts can be supported by programming the following registers. More interrupt sources can be supported by external daisy-chaining. The interrupt inputs are internally synchronized. Edge-triggered interrupts are not supported. ...
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... Freescale Semiconductor, Inc Autovector. 5.2.4.2 INTERRUPT STATUS REGISTER. An enabled, active interrupt appears as a one in the interrupt status register, regardless of the active voltage level programmed at reset. This register is read-only, writes to this register are ignored. FFFFFFF8 IRQT IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 RESE ...
Page 97
... Freescale Semiconductor, Inc. Port B pins can be individually programmed as either IRQ, IACK or parallel port signals. To use any of the port B pins PB7–PB4 as interrupt request signals (IRQ6, IRQ5, IRQ3, IRQ2) be sure the bit is programmed as an input. Interrupt enables are provided for each interrupt level. ...
Page 98
... Freescale Semiconductor, Inc. This bit determines the direction of data flow at port B pins 7– Input Output. 5.2.5.3 PORT DATA REGISTER. The port data register bits return the value as written, regardless of the direction register and pin state. For pins configured as outputs, the corresponding value in the port data register is driven externally. ...
Page 99
... Freescale Semiconductor, Inc. Unused chip selects must be disabled to prevent interference with other chip selects, DRAM, or externally decoded resources. There are three ways to disable a chip select, corresponding to the three match conditions: 1. All CSFCx bits are zero 2. Both CSW/CSR are zero 3. Any unused CSAx bit is one. ...
Page 100
... Freescale Semiconductor, Inc. CSW—Chip Select Write This bit determines whether write cycles are permitted to chip select space. If read and write cycles are both inhibited, chip select is inhibited Write cycles are inhibited to chip select space 1 = Write cycles are permitted to chip select space 5 ...
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... Freescale Semiconductor, Inc. ......... 1111 = A31–A17 must match CSA31–CSA17 in chip select address match Table 5-2 shows the entire range of address bits that must match for a chip select to occur. Table 5-2. Chip Select Match Bits A31 A30 A29 A28 0000 0001 • ...
Page 102
... Freescale Semiconductor, Inc. Figure 5-1 shows a method of expanding the number of chip selects in case more are required for the application. MC68306 ADDR AMODE } CS0 CS1 CS2 1 MBYTE ADDRESS CS3 SPACE EACH CS4 CS5 CS6 CS7 Figure 5-1. Chip Select Expansion 5.2.7 DRAM Control Registers The DRAM address space decode mechanism is identical to the chip select mechanism ...
Page 103
... Freescale Semiconductor, Inc. 68306 regains bus ownership. Only one refresh cycle occurs after bus ownership is regained, regardless of the time the bus was granted away. The DRAM controller provides RAS/CAS timing, 15 multiplexed address bits, and refresh timing. All DRAM accesses are either zero or one wait state cycles, unless delayed by a refresh ...
Page 104
... Freescale Semiconductor, Inc. 5.2.7.1 DRAM REFRESH REGISTER. The refresh timer is a programmable period counter that generates a refresh request every 16 to 4096 EXTAL periods, programmable in 16 EXTAL period increments. FFFFFFFC 15 RR7 RESET : U RR7–0—Refresh Rate Period The value set in this field supplies the refresh rate for the DRAM controller. The refresh ...
Page 105
... Freescale Semiconductor, Inc. 5.2.7.3 DRAM BANK CONFIGURATION REGISTER (LOW HALF) FFFFFFE6/7 (DR1), FFFFFFE2/3 (DR0 DRR DRFC DRFC — — DRFC 6 5 RESE DRR—DRAM Read This bit determines whether read cycles are permitted to DRAM bank space. If read and write cycles are both inhibited, DRAM bank is inhibited. ...
Page 106
... Freescale Semiconductor, Inc. Table 5-4. DRAM Bank Match Bits A31 A30 A29 A28 0000 0001 • 0010 • • 0011 • • • x 0100 • • • • 0101 • • • • 0110 • • • • 0111 • • ...
Page 107
... Freescale Semiconductor, Inc. DTACK 5.2.8 Automatic All eight chip selects and both DRAM banks can be independently programmed for automatic DTACK generation . Chip select accesses can be programmed for wait states or external DTACK, supporting memories as slow as 960 ns (at 16.67 MHz) with no external logic. Programming the automatic DTACK for chip selects is described in paragraph 5 ...
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... Freescale Semiconductor, Inc. EXTAL Figure 5-2. Oscillator Circuit Diagram 5-18 For More Information On This Product EXT MC68306 MC68306 USER'S MANUAL Go to: www.freescale.com XTAL MOTOROLA ...
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... Freescale Semiconductor, Inc. SECTION 6 SERIAL MODULE The MC68306 serial module is a dual universal asynchronous/synchronous receiver/ transmitter that interfaces directly to the CPU. The serial module, shown in Figure 6-1, consists of the following major functional areas: • Two Independent Serial Communication Channels (A and B) • Baud Rate Generator Logic • ...
Page 110
... Freescale Semiconductor, Inc. 6.1 MODULE OVERVIEW Features of the serial module are as follows: • Two, Independent, Full-Duplex Asynchronous/Synchronous Receiver/Transmitter Channels • Quadruple-Buffered Receiver • Double-Buffered Transmitter • Independently Programmable Baud Rate for Each Receiver and Transmitter Selectable from: —18 Fixed Rates 38.4 kBaud — ...
Page 111
... Freescale Semiconductor, Inc. 6.1.1 Serial Communication Channels A and B Each communication channel provides a full-duplex asynchronous/synchronous receiver and transmitter using an operating frequency independently selected from a baud rate generator or an external clock input. The transmitter accepts parallel data from the bus, converts serial bit stream, inserts the appropriate start, stop, and optional parity bits, then outputs a composite serial data stream on the channel transmitter serial data output (TxDx) ...
Page 112
... Freescale Semiconductor, Inc. The TIRQ interrupt (if enabled) is fixed at level seven. When a level seven interrupt is acknowledged, the TIRQ interrupt is serviced before the external IRQ7. If the serial module IRQ is also programmed at level seven, the TIRQ interrupt is serviced first, then the serial module IRQ, then the external IRQ7 last. ...
Page 113
... Freescale Semiconductor, Inc. ADDRESS BUS INTERNAL CONTROL CONTROL LOGIC INTERFACE TO CPU DATA D7–D0 TIRQ IRQ Figure 6-2. External and Internal Interface Signals 6.2.4 Channel A Receiver Serial Data Input (RxDA) This signal is the receiver serial data input for channel A. Data received on this signal is sampled on the rising edge of the clock source, with the least significant bit received first ...
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... Freescale Semiconductor, Inc. 6.2.6 Channel B Receiver Serial Data Input (RxDB) This signal is the receiver serial data input for channel B. Data on this signal is sampled on the rising edge of the clock source, with the least significant bit received first. 6.2.7 Channel A Request-To-Send ( This active-low output signal is programmable as the channel A request-to-send dedicated parallel output ...
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... Freescale Semiconductor, Inc. 6.3 OPERATION The following paragraphs describe the operation of the baud rate generator, transmitter and receiver, and other functional operating modes of the serial module. 6.3.1 Baud Rate Generator The baud rate generator consists of a crystal oscillator, baud rate generator, and clock selectors (see Figure 6-3) ...
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... Freescale Semiconductor, Inc. TRANSMIT BUFFER (TBA) (2 REGISTERS) RECEIVE BUFFER (RBA) (4 REGISTERS) TRANSMIT BUFFER (TBB) (2 REGISTERS) RECEIVE BUFFER (RBB) (4 REGISTERS) NOTE: R/W = READ/WRITE R = READ W = WRITE . . . . . . Figure 6-4. Transmitter and Receiver Functional Diagram 6-8 For More Information On This Product, CHANNEL A COMMAND REGISTER (CRA) ...
Page 117
... Freescale Semiconductor, Inc. 6.3.2.1 TRANSMITTER. The transmitters are enabled through their respective command registers (DUCR) located within the serial module. The serial module signals the CPU when it is ready to accept a character by setting the transmitter-ready bit (TxRDY) in the channel's status register (DUSR). Functional timing information for the transmitter is shown in Figure 6-5 ...
Page 118
... Freescale Semiconductor, Inc. transmit shift register, if any, is completely sent out. If the transmitter is reset through a software command, operation ceases immediately (refer to 6.4.1.5 Command Register (DUCR)). The transmitter is re-enabled through the DUCR to resume operation after a disable or software reset. If clear-to-send operation is enabled, CTS≈ (IP0 for channel A, IP1 for channel B) must be asserted for the character to be transmitted. If CTS≈ ...
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... Freescale Semiconductor, Inc RxD RECEIVER ENABLED RxRDY (SR0) FFULL (SR1 STATUS DATA C1 OVERRUN (SR4) 1 RTS (OP0) OPR( NOTES: 1. Timing shown for MR1( Timing shown for OPCR( and MR1( Read Received Character N Figure 6-6. Receiver Timing Diagram The receiver detects the beginning of a break in the middle of a character if the break persists through the next character time ...
Page 120
... Freescale Semiconductor, Inc. register position of the FIFO. Thus, data flowing from the receiver to the CPU is quadruple buffered. In addition to the data byte, three status bits, PE, FE, and RB, are appended to each data character in the FIFO not appended. By programming the ERR bit in the channel's mode register (DUMR1), status is provided in character or block modes ...
Page 121
... Freescale Semiconductor, Inc. 6.3.3 Looping Modes Each serial module channel can be configured to operate in various looping modes as shown in Figure 6-7. These modes are useful for local and remote system diagnostic functions. The modes are described in the following paragraphs with further information available in 6.4 Register Description and Programming. ...
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... Freescale Semiconductor, Inc. CPU DISABLED CPU DISABLED CPU DISABLED Figure 6-7. Looping Modes Functional Diagram 6.3.4 Multidrop Mode A channel can be programmed to operate in a wakeup mode for multidrop or multiprocessor applications. Functional timing information for the multidrop mode is shown in Figure 6-8. The mode is selected by setting bits 3 and 4 in mode register 1 (DUMR1). ...
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... Freescale Semiconductor, Inc. MASTER STATION TxD ADDR 1 TRANSMITTER ENABLED TxRDY (SR2 MR1(4: ADDR1 MR1( MR1( PERIPHERAL STATION A/D RxD ADDR 0 1 RECEIVER ENABLED CS W MR1(4– Figure 6-8. Multidrop Mode Timing Diagram A transmitted character from the master station consists of a start bit, a programmed number of data bits, an address/data (A/D) bit flag, and a programmed number of stop bits ...
Page 124
... Freescale Semiconductor, Inc. In either case, the data bits are loaded into the data portion of the stack while the A/D bit is loaded into the status portion of the stack normally used for a parity error (DUSR bit 5). Framing error, overrun error, and break detection operate normally. The A/D bit takes the place of the parity bit ...
Page 125
... Freescale Semiconductor, Inc. can be programmed to appear on output pin OP3 (inverted). The timer runs continuously and cannot be stopped by the CPU. Because the timer cannot be stopped, the count value (DUCUR/DUCLR) should not be read. When a read at the start counter command address is performed, the timer terminates the current countdown sequence, clears its output, reinitializes itself with the preload value, and begins a new countdown sequence ...
Page 126
... Freescale Semiconductor, Inc. shown in Figure 6-9. The mode, status, command, and clock-select registers are duplicated for each channel to provide independent operation and control. All serial module registers are only accessible as bytes. The contents of the mode registers (DUMR1 and DUMR2), clock- select register (DUCSR), and the auxiliary control register (DUACR) bit 7 should only be changed after the receiver/transmitter is issued a software RESET command— ...
Page 127
... Freescale Semiconductor, Inc. channel A mode register pointer points to DUMR1. The pointer is set to DUMR1 by RESET set pointer command, using control register A. After reading or writing DUMR1A, the pointer points to DUMR2A. DUMR1A, DUMR1B 7 RxRTS RxIRQ RESET: 0 Read/Write RxRTS—Receiver Request-to-Send Control 1 = Upon receipt of a valid start bit, RTS≈ is negated if the channel's FIFO is full. ...
Page 128
... Freescale Semiconductor, Inc. PT—Parity Type This bit selects the parity type if parity is programmed by the parity mode bits, and if multidrop mode is selected, it configures the transmitter for data character transmission or address character transmission. Table 6-1 lists the parity mode and type or the multidrop mode for each combination of the parity mode and the parity type bits. ...
Page 129
... Freescale Semiconductor, Inc. TxRTS—Transmitter Ready-to-Send This bit controls the negation of the RTSA or RTSB signals. The output is normally asserted by setting OP0 or OP1 and negated by clearing OP0 or OP1 (see 6.4.1.18 Output Port Control Register (DUOPCR)). applications where the transmitter is disabled after transmission is complete, ...
Page 130
... Freescale Semiconductor, Inc. SB3 SB2 6.4.1.3 STATUS REGISTER (DUSR). The DUSR indicates the status of the characters in the FIFO and the status of the channel transmitter and receiver. DUSRA, DUSRB 7 RB RESET: 0 Read Only RB—Received Break all-zero character of the programmed length has been received without a stop bit ...
Page 131
... Freescale Semiconductor, Inc. FE—Framing Error stop bit was not detected when the corresponding data character in the FIFO was received. The stop-bit check is made in the middle of the first stop-bit position. The bit is valid only when the RxRDY bit is set framing error has occurred. ...
Page 132
... Freescale Semiconductor, Inc. RxRDY—Receiver Ready 1 = One or more characters has been received in channel B and is waiting in the receiver buffer FIFO The CPU has read the receiver buffer, and no characters remain in the FIFO after this read. 6.4.1.4 CLOCK-SELECT REGISTER (DUCSR). The DUCSR selects the baud rate clock for the channel receiver and transmitter ...
Page 133
... Freescale Semiconductor, Inc. RCS3 TCS3–TCS0—Transmitter Clock Select These bits select the baud rate clock for the channel transmitter from a set of baud rates listed in Table 6-6 The baud rate set selected depends upon DUACR bit 7. Set 1 is selected if DUACR bit and set 2 is selected if DUACR bit The transmitter clock is always 16 times the baud rate shown in this list, except when the clock select bits = 1111 ...
Page 134
... Freescale Semiconductor, Inc. TCS3 6.4.1.5 COMMAND REGISTER (DUCR). The DUCR is used to supply commands to the channel. Multiple commands can be specified in a single write to the DUCR if the commands are not conflicting—e.g., reset transmitter and enable transmitter commands cannot be specified in a single command. ...
Page 135
... Freescale Semiconductor, Inc. MISC2 MISC1 Reset Mode Register Pointer—The reset mode register pointer command causes the mode register pointer to point to DUMR1. Reset Receiver—The reset receiver command resets the channel receiver. The receiver is immediately disabled, the FFULL and RxRDY bits in the DUSR are cleared, and the receiver FIFO pointer is reinitialized ...
Page 136
... Freescale Semiconductor, Inc. No Action Taken—The no action taken command causes the transmitter to stay in its current mode. If the transmitter is enabled, it remains enabled; if disabled, it remains disabled. Transmitter Enable—The transmitter enable command enables operation of the channel's transmitter. The TxEMP and TxRDY bits in the DUSR are also set. If the transmitter is already enabled, this command has no effect. Transmitter Disable— ...
Page 137
... Freescale Semiconductor, Inc. local loopback mode or multidrop mode, the receiver operates even though this command is selected. If the receiver is already disabled, this command has no effect. Do Not Use—Do not use this bit combination because the result is indeterminate. 6.4.1.6 RECEIVER BUFFER (DURB). The receiver buffer contains three receiver holding registers and a serial shift register ...
Page 138
... Freescale Semiconductor, Inc. Bits 2—Reserved COS2, COS1, COS0—Change-of-State change-of-state (high-to-low or low-to-high transition), lasting longer than 25– has occurred at the corresponding IPx input. When these bits are set, the DUACR can be programmed to generate an interrupt to the CPU change-of-state has occurred since the last time the CPU read the DUIPCR. ...
Page 139
... Freescale Semiconductor, Inc. Table 6-10. Counter/Timer Mode and Source Select Bits MISC2 MISC1 MISC0 IEC2, IEC1, IEC0—Input Enable Control 1 = DUISR bit 7 will be set and an interrupt will be generated when the corresponding bit in the DUIPCR (COS2, COS1, or COS0) is set by an external transition on the IPx input (if bit 7 of the interrupt mask register (DUIMR) is set to enable interrupts) ...
Page 140
... Freescale Semiconductor, Inc. DBB—Delta Break The channel B receiver has detected the beginning or end of a received break new break-change condition to report. Refer to 6.4.1.5 Command Register (DUCR) for more information on the reset break-change interrupt command. RxRDYB—Channel B Receiver Ready or FIFO Full The function of this bit is programmed by DUMR1B bit duplicate of either the FFULL or RxRDY bit of DUSRB. TxRDYB— ...
Page 141
... Freescale Semiconductor, Inc. DBB—Delta Break Enable interrupt 0 = Disable interrupt FFULLB—Channel B FIFO Full 1 = Enable interrupt 0 = Disable interrupt TxRDYB, TxRDYA—Transmitter Ready 1 = Enable interrupt 0 = Disable interrupt CTR/TMR_RDY—Counter/Timer Ready 1 = Enable interrupt 0 = Disable interrupt DBA—Delta Break Enable interrupt 0 = Disable interrupt FFULLA—Channel A FIFO Full ...
Page 142
... Freescale Semiconductor, Inc. 6.4.1.16 INTERRUPT VECTOR REGISTER (DUIVR). The DUIVR contains the 8-bit vector number of the IRQ interrupt. DUIVR 7 IVR7 RESET: 0 Read /Write IVR7–IVR0—Interrupt Vector Bits Each module that generates interrupts can have an interrupt vector field. This 8-bit number indicates the offset from the base of the vector table where the address of the exception handler for the specified interrupt is located ...
Page 143
... Freescale Semiconductor, Inc. DUOPCR 7 OP7 T≈RDYB T≈RDYA RESET: 0 Write Only OP bits and 2 are not pinned out on the MC68306; thus changing bits and 0 of this register has no effect. OPCR3–OPCR2—Output Port 3 Function Select 00 = OPR bit Counter/timer output 10 = TxCB (1X RxCB (1X) OP3 is open-drain in this mode, and an external pullup is required. OPCR1– ...
Page 144
... Freescale Semiconductor, Inc. 6.4.1.19 OUTPUT PORT DATA REGISTER (DUOP). The bits in the DUOP register are set by performing a bit set command (writing to $FFFFF7FD) and are cleared by performing a bit reset command (writing to offset $FFFFF7FF). DUOP 7 OP7 RESET: 0 Write Only The output port bits are inverted at the pins. ...
Page 145
... Freescale Semiconductor, Inc. 6.4.2 Programming The basic interface software flowchart required for operation of the serial module is shown in Figure 6-10. The routines are divided into three categories: • Serial Module Initialization • I/O Driver • Interrupt Handling 6.4.2.1 SERIAL MODULE INITIALIZATION. The serial module initialization routines consist of SINIT and CHCHK ...
Page 146
... Freescale Semiconductor, Inc. SERIAL MODULE SINIT INITIATE: CHANNEL A CHANNEL B INTERRUPTS CHK1 POINT TO CHANNEL A CALL CHCHK SAVE CHANNEL A STATUS CHK2 POINT TO CHANNEL B CALL CHCHK SAVE CHANNEL B STATUS Figure 6-10. Serial Module Programming Flowchart ( 6-38 For More Information On This Product, ENABLA ANY ERRORS IN ...
Page 147
... Freescale Semiconductor, Inc. CHCHK CHCHK PLACE CHANNEL IN LOCAL LOOPBACK MODE ENABLE CHANNEL'S TRANSMITTER CLEAR CHANNEL STATUS WORD TxCHK IS N TRANSMITTER READY ? Y SNDCHR SEND CHARACTER TO TRANSMITTER RxCHK HAS RECEIVER N RECEIVED CHARACTER ? Y A Figure 6-10. Serial Module Programming Flowchart ( MOTOROLA For More Information On This Product, ...
Page 148
... Freescale Semiconductor, Inc. A FRCHK HAVE FRAMING ERROR ? Y SET FRAMING ERROR FLAG PRCHK HAVE PARITY ERROR ? Y SET PARITY ERROR FLAG A CHRCHK GET CHARACTER FROM RECEIVER SAME AS CHARACTER TRANSMITTED ? N SET INCORRECT CHARACTER FLAG B Figure 6-10. Serial Module Programming Flowchart ( 6-40 For More Information On This Product, ...
Page 149
... Freescale Semiconductor, Inc. SIRQ ABRKI WAS IRQx CAUSED BY BEGINNING OF A BREAK ? Y CLEAR CHANGE-IN- BREAK STATUS BIT ABRKI1 HAS END-OF-BREAK IRQx ARRIVED YET ? Y CLEAR CHANGE-IN- BREAK STATUS BIT REMOVE BREAK CHARACTER FROM RECEIVER FIFO REPLACE RETURN ADDRESS ON SYSTEM STACK AND MONITOR WARM START ADDRESS ...
Page 150
... Freescale Semiconductor, Inc. Figure 6-10. Serial Module Programming Flowchart ( 6-42 For More Information On This Product, OUTCH IS CHANNEL N TRANSMITTER READY ? Y SEND CHARACTER TO CHANNEL TRANSMITTER RETURN MC68306 USER'S MANUAL Go to: www.freescale.com MOTOROLA ...
Page 151
... Freescale Semiconductor, Inc. 6.5 SERIAL MODULE INITIALIZATION SEQUENCE If the serial capability of the MC68306 is being used, the following steps are required to properly initialize the serial module. The serial module registers can be accessed by word or byte operations, but only the data byte D7–D0 is valid. ...
Page 152
... Freescale Semiconductor, Inc. • If desired, program operation of clear-to-send (TxCTS bit). • Select stop-bit length (SBx bits). Command Register (DUCR) • Enable the receiver and transmitter. 6-44 For More Information On This Product, MC68306 USER'S MANUAL Go to: www.freescale.com MOTOROLA ...
Page 153
... Freescale Semiconductor, Inc. SECTION 7 IEEE 1149.1 TEST ACCESS PORT The MC68306 includes dedicated user-accessible test logic that is fully compatible with the IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture . Problems associated with testing high-density circuit boards have led to development of this standard under the sponsorship of the Test Technology Committee of IEEE and the Joint Test Action Group (JTAG) ...
Page 154
... Freescale Semiconductor, Inc. An overview of the MC68306 implementation of IEEE 1149.1 is shown in Figure 7-1. The MC68306 implementation includes a 16-state controller, a 3-bit instruction register, and four test registers (a 1-bit bypass register, a 124-bit boundary scan register, a 3-bit module mode register, and a 32-bit ID register). This implementation includes a dedicated TAP consisting of the following signals: TRST — ...
Page 155
... Freescale Semiconductor, Inc. 7.2 TAP CONTROLLER The TAP controller is responsible for interpreting the sequence of logical values on the TMS signal synchronous state machine that controls the operation of the JTAG logic. The state machine is shown in Figure 7-2; the value shown adjacent to each arc represents the value of the TMS signal sampled on the rising edge of the TCK signal ...
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... Freescale Semiconductor, Inc. The XTAL and X2 pins are associated with analog signals and are not included in the boundary scan register. All MC68306 bidirectional pins, except the open-drain I/O pins (HALT, DTACK, BERR, and RESET ), have a single register bit for pin data and an associated control bit in the boundary scan register ...
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... Freescale Semiconductor, Inc. Table 7-2. Boundary Scan Bit Definitions Bit Num Cell Type Signal 0 O.Cell OP1 1 O.Cell OP0 2 I.Cell IP1 3 I.Cell IP0 4 O.Cell TXDB 5 I.Cell RXDB 6 O.Cell TXDA 7 I.Cell RXDA 8 En.Cell OPOE3 9 O.Cell OP3 10 I.Cell IP2 11 I.Cell X1 12 En.Cell PPOE8 13 IO.Cell ...
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... Freescale Semiconductor, Inc. Table 7-2. Boundary Scan Bit Definitions (Continued) Bit Cell Type Num Signal 68 IO.Cell BERR 69 IO.Cell DTACK 70 IO.Cell FC0 71 IO.Cell FC1 72 IO.Cell FC2 73 IOx0.Cell RESET 74 IOx0.Cell HALT 75 O.Cell CLKOUT 76 I.Cell BR 77 O.Cell BG 78 I.Cell BGACK 79 IO.Cell AS 80 IO.Cell IO.Cell ...
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... Freescale Semiconductor, Inc. 1 – EXTEST 0 – OTHERWISE SHIFT DR G1 DATA FROM SYSTEM 1 LOGIC MUX 1 Figure 7-3. Output Cell (O.Cell) TO DEVICE LOGIC TO NEXT CELL MOTOROLA For More Information On This Product, TO NEXT CELL MUX 1 C1 FROM CLOCK DR UPDATE DR LAST CELL G1 1 MUX CLOCK DR ...
Page 160
... Freescale Semiconductor, Inc. 1 – EXTEST 0 – OTHERWISE G1 OUTPUT CONTROL 1 FROM MUX SYSTEM LOGIC 1 SHIFT DR Figure 7-5. Output Control Cell (En.Cell) 1 – EXTEST 0 – OTHERWISE G1 OUTPUT FROM 1 SYSTEM MUX LOGIC 1 FROM PIN INPUT TO SYSTEM LOGIC Figure 7-6. Bidirectional Cell (IO.Cell) 7-8 For More Information On This Product, ...
Page 161
... Freescale Semiconductor, Inc. 1 – EXTEST 0 – OTHERWISE G1 OUTPUT FROM 1 SYSTEM MUX LOGIC 1 FROM PIN Figure 7-7. Bidirectional Cell (IOx0.Cell) TO NEXT CELL OUTPUT ENABLE OUTPUT DATA INPUT DATA FROM LAST CELL NOTE: More than one lO.Cell could be serially connected and controlled by a single En.Cell. ...
Page 162
... Freescale Semiconductor, Inc. MC68306 includes a 3-bit instruction register without parity, consisting of a shift register with three parallel outputs. Data is transferred from the shift register to the parallel outputs during the update-IR controller state. The three bits are used to decode the six unique instructions listed in Table 7-3 ...
Page 163
... Freescale Semiconductor, Inc. Since there is no internal synchronization between the IEEE 1149.1 clock (TCK) and the system clock (CLKOUT), the user must provide some form of external synchronization to achieve meaningful results. The second function of SAMPLE/PRELOAD is to initialize the boundary scan register output bits prior to selection of EXTEST. This initialization ensures that known data will appear on the outputs when entering the EXTEST instruction ...
Page 164
... Freescale Semiconductor, Inc. Also, the MC68306 contains dynamic logic, so EXTAL must be driven by a free-running clock at all times. 7.6 NON-IEEE 1149.1 OPERATION In non-IEEE 1149.1 operation, the IEEE 1149.1 test logic must be kept transparent to the system logic by forcing the TAP controller into the test-logic-reset state. This requires either: 1 ...
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... Freescale Semiconductor, Inc. SECTION 8 ELECTRICAL CHARACTERISTICS This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications of the MC68306. Refer to Section 9 Ordering Information and Mechanical Data for specific part numbers corresponding to voltage, frequency, and temperature ratings. 8.1 MAXIMUM RATINGS ...
Page 166
... Freescale Semiconductor, Inc. 8.3 POWER CONSIDERATIONS The average chip-junction temperature can be obtained from: where Ambient Temperature Package Thermal Resistance, Junction-to-Ambient, C INT + P I/O P INT = Watts—Chip Internal Power P I/O = Power Dissipation on Input and Output Pins—User Determined For most applications, P I/O < P INT and can be neglected. ...
Page 167
... Freescale Semiconductor, Inc. 2.0 V CLKOUT B 2.0 V VALID OUTPUTS(1) OUTPUT n 0.8 V OUTPUTS(2) INPUTS(3) INPUTS(4) ALL SIGNALS(5) NOTES: 1. This output timing is applicable to all parameters specified relative to the rising edge of the clock. 2. This output timing is applicable to all parameters specified relative to the falling edge of the clock. ...
Page 168
... Freescale Semiconductor, Inc. 8.5 DC ELECTRICAL SPECIFICATIONS (The electrical specifications in this document are preliminary) Characteristic Input High Voltage (except clock) Input Low Voltage Clock Input High Voltage Input Leakage Current (All Input Only Pins) Three-State (Off State) Input Current @ 2.4 V/0.4 V Output High Voltage ...
Page 169
... Freescale Semiconductor, Inc. 3.8 V 1.5 V 0.8 V EXTAL 4 1A CLKOUT NOTE: Timing measurements are referenced to and from a low voltage of 0.8 V and a high voltage of 3.8 V, unless otherwise noted. The voltage swing through this range should start outside and pass through the range such that the rise or fall will be linear between 0 ...
Page 170
... Freescale Semiconductor, Inc. 8.7 AC ELECTRICAL SPECIFICATIONS—READ AND WRITE CYCLES (Continued) Num Characteristic 6 20A AS Asserted to R/W Low (Write Address Valid to R/W Low (Write) 2 21A FC Valid to R/W Low (Write Low to LDS, UDS Asserted (Write) 23 CLKOUT Low to Data-Out Valid (Write AS, LDS, UDS Negated to Data-Out Invalid (Write) ...
Page 171
... Freescale Semiconductor, Inc. S0 CLKOUT FC2–FC0 A23– LDS / UDS R/W OE DTACK DATA IN BERR / BR (NOTE 2) HALT / RESET ASYNCHRONOUS INPUTS (NOTE 1) NOTES: 1. Setup time (#47) for asynchronous inputs (HALT, RESET, BR, BGACK, DTACK, BERR, IRQx) guarantees their recognition at the next falling edge of the clock. ...
Page 172
... Freescale Semiconductor, Inc. S0 CLKOUT FC2–FC0 A23– (NOTE 2) LDS / UDS 17 R/W (NOTE 2) 13 UW, LW DTACK DATA OUT BERR / BR (NOTE 3) HALT / RESET ASYNCHRONOUS INPUTS (NOTE 1) NOTES: 1. Setup time (#47) for asynchronous inputs (HALT, RESET, BR, BGACK, DTACK, BERR, IRQx) guarantees their recognition at the next falling edge of the clock. ...
Page 173
... Freescale Semiconductor, Inc. 8.8 AC ELECTRICAL SPECIFICATIONS—CHIP SELECTS AND INTERRUPT ACKNOWLEDGE Num 61 Address Valid to CS≈ Asserted (Read or Write) 61A FC Valid to CS≈ Asserted (Read or Write CS≈ CS≈ 64 CS≈ Width Asserted 65 CS≈ Negated to FC, Addess Invalid 66 CS≈ Negated Invalid 67 Data-Out Valid to CS≈ ...
Page 174
... Freescale Semiconductor, Inc. 8.9 AC ELECTRICAL SPECIFICATIONS—BUS ARBITRATION specifications in this document are preliminary. See Figures 8-6–8-7) Num Characteristic 7 CLKOUT High to Address, Data Bus High Impedance (Maximum) 16 CLKOUT High to Control Bus High Impedance 33 CLKOUT High to BG Asserted 34 CLKOUT High to BG Negated ...
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... Freescale Semiconductor, Inc. Figure 8-7. Bus Arbitration Timing Diagram MOTOROLA For More Information On This Product, MC68306 USER'S MANUAL Go to: www.freescale.com 8- 11 ...
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... Freescale Semiconductor, Inc. 8.10 BUS OPERATION—DRAM ACCESSES AC TIMING SPECIFICATIONS (The electrical specifications in this document are preliminary. See Figures 8-8–8-11) Num. Characteristic 71 CLKOUT High to RAS≈ Asserted (0 Wait State Operation) 71A AS Asserted to RAS≈ Asserted (0 Wait State Operation) 72 CLKOUT Low to RAS≈ Asserted (1 Wait State Operation) ...
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... Freescale Semiconductor, Inc. CLKOUT FC0–FC2 A15/DRAMA 14– A1/DRAMA 0 AS UDS, LDS R/W UW DTACK D15–D0 DRAMW RAS CAS Figure 8-8. DRAM Timing – 0-Wait Read, No Refresh MOTOROLA For More Information On This Product 71A MC68306 USER'S MANUAL Go to: www.freescale.com 87 89 89A ...
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... Freescale Semiconductor, Inc. CLKOUT FC0–FC2 A15/DRAMA 14– A1/DRAMA 0 AS UDS, LDS R/W UW DTACK D15–D0 DRAMW RAS CAS Figure 8-9. DRAM Timing – 1-Wait Write, No Refresh 1-WAIT STATE CLKOUT 102 DRAMW 103 99 RAS CAS Figure 8-10. DRAM Timing – 0- and 1-Wait Refresh ...
Page 179
... Freescale Semiconductor, Inc. CLKOUT FC0–FC2 A15/DRAMA 14– A1/DRAMA 0 AS UDS, LDS R/W UW DTACK D15–D0 DRAMW RAS 80 CAS 90 * NOTE: TAS IS A BYTE-ONLY INSTRUCTION, THEREFORE ONLY ONE OF UW, LW AND ONLY ONE CAS WILL BE ASSERTED. Figure 8-11. DRAM Timing – 1-Wait, Test and Set 8 ...
Page 180
... Freescale Semiconductor, Inc. 8.12 SERIAL MODULE AC ELECTRICAL CHARACTERISTICS—CLOCK TIMING (See Figure 8-12.) Characteristic Counter/Timer Clock High or Low Time Clock Rise Time Clock Fall Time IP2 FOR C/T CLK 8.13 AC ELECTRICAL CHARACTERISTICS—PORT TIMING (See Figure 8-13 and Note.) Characteristic Port Input Setup Time to LDS Asserted ...
Page 181
... Freescale Semiconductor, Inc. 8.14 AC ELECTRICAL CHARACTERISTICS—INTERRUPT RESET TIMING (See Figure 8-14 and Note) Characteristic OP3 High (When Used as Counter Interrupt) from LDS Negated After Stop Counter Command NOTE: Test conditions for interrupt output pF LDS * OP3 * When used as counter interrupt output. ...
Page 182
... Freescale Semiconductor, Inc. 8.16 AC ELECTRICAL CHARACTERISTICS—RECEIVER TIMING (See Figure 8-16 and Note) Characteristic RxD Data Setup Time to RxC High RxD Data Hold Time from RxC High RTS Output Valid from Rx Clock Rx CLOCK SOURCE (X1 OR IP2) RxD * OP0, OP1 * When used as RxRTS ...
Page 183
... Freescale Semiconductor, Inc. 8.17 IEEE 1149.1 ELECTRICAL CHARACTERISTICS (The electrical specifications in this document are preliminary; see Figures 8-17–8-19.) Num. Characteristic TCK Frequency of Operation 1 TCK Cycle Time 2 TCK Clock Pulse Width Measured at 1 TCK Rise and Fall Times 6 Boundary Scan Input Data Setup Time ...
Page 184
... Freescale Semiconductor, Inc. TCK V IL DATA INPUTS DATA OUTPUTS DATA OUTPUTS DATA OUTPUTS Figure 8-18. Boundary Scan Timing Diagram TCLK TDI TMS TDO TDO TDO Figure 8-19. Test Access Port Timing Diagram 8-20 For More Information On This Product, 6 INPUT DATA VALID ...
Page 185
... Freescale Semiconductor, Inc. SECTION 9 ORDERING INFORMATION AND MECHANICAL DATA This section contains the ordering information, pin assignments, and package dimensions for the MC68306. 9.1 STANDARD ORDERING INFORMATION Package Type 132-Lead Plastic Quad Flat Pack (FC Suffix) 144-Lead Thin Quad Flat Pack (PV Suffix) ...
Page 186
... Freescale Semiconductor, Inc. 9.2 PIN ASSIGNMENTS 132-Lead Plastic Quad Flat Pack (PQFP A21/CS5 A20/CS4 CS3 CS2 GND CS1 CS0 CAS0 CAS1 RAS0 VDD RAS1 DRAMW GND LDS UDS R/W AS BGACK VDD BG BR EXTAL XTAL CLKOUT GND HALT RESET FC2 N 9-2 For More Information On This Product, ...
Page 187
... Freescale Semiconductor, Inc. 144-Lead Thin Quad Flat Pack (TQFP) 144 N/C 1 N/C A21/CS5 A20/CS4 CS3 CS2 GND CS1 CS0 CAS0 CAS1 RAS0 VCC RAS1 DRAMW GND LDS UDS R/W AS BGACK VCC BG BR EXTAL XTAL CLKOUT GND HALT RESET FC2 N/C N/C ...
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... Freescale Semiconductor, Inc. 9.3 PACKAGE DIMENSIONS 132 Pin PQFP (FC Suffix) CASE 831A-01 T 0.25 (0.010 0.05 (0.002 0.25 (0.010) 0.05. (0.002) C .10 (0.004) T SEATING PLANE MILLIMETERS DIM MIN MAX MIN A 24.06 24.20 0.947 B 24.06 24.20 0.947 C 4.07 4.57 0.160 D 0.21 0.30 0.008 G 0 ...
Page 189
... Freescale Semiconductor, Inc. 144-Lead Thin Quad Flat Pack (PV Suffix) MOTOROLA For More Information On This Product, MC68306 USER'S MANUAL Go to: www.freescale.com 9- 5 ...
Page 190
... Freescale Semiconductor, Inc. — A — Access Error, 4-1 Exception, 4-21 Addressing Modes, 4-4 Index Sizing and Scaling, 4-4 Indexing, 4-4 Postincrement, Predecrement, Offset, and Program Counter Indirect, 4-4 Register Indirect, 4-4 AS, 3-4, 3-7, 3-16 Asynchronous Bus Arbitration Signals, 3-17 Asynchronous Mode, 3-32 ...
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... Freescale Semiconductor, Inc. — J — JTAG, 7-1 — L — LDS, 3-7 Level 7 Interrupts, 4-17 Looping Modes, 6-13 — N — Non-IEEE 1149.1 Operation, 7-12 — O — Operand Size, 4-3 Oscillator Circuit, 5-16 — P — Package Dimensions, 9-1 Pin Assignments, 9-1 Port Data Register, 5-8 ...