MC68020RC25E Freescale Semiconductor, MC68020RC25E Datasheet - Page 208

• Manufacturer Part Number: MC68020RC25E
• Description: IC MICROPROC 32-BIT 25MHZ 114PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68020RC25E

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 114-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Other names: Q1165253

Freescale Semiconductor, Inc.
When the MC68020/EC020 detects a protocol violation, it does not automatically notify the
coprocessor of the resulting exception by writing to the control CIR. However, the
exception handling routine may use the MOVES instruction to read the response CIR and
thus determine the primitive that caused the MC68020/EC020 to initiate protocol violation
exception processing. The main processor initiates exception processing using the
midinstruction stack frame (refer to Figure 7-43) and the coprocessor protocol violation
exception vector number 13. If the exception handler does not modify the stack frame, the
main processor reads the response CIR again following the execution of an RTE
instruction to return from the exception handler. This protocol allows extensions to the
M68000 coprocessor interface to be emulated in software by a main processor that does
not provide hardware support for these extensions. Thus, the protocol violation is
transparent to the coprocessor if the primitive execution can be emulated in software by
the main processor.
7.5.2.2 F-LINE EMULATOR EXCEPTIONS. The F-line emulator exceptions detected by
the MC68020/EC020 are either explicitly or implicitly related to the encodings of F-line
operation words in the instruction stream. If the main processor determines that an F-line
operation word is not valid, it initiates F-line emulator exception processing. Any F-line
operation word with bits 8–6 = 110 or 111 causes the MC68020/EC020 to initiate
exception processing without initiating any communication with the coprocessor for that
instruction. Also, an operation word with bits 8–6 = 000–101 that does not map to one of
the valid coprocessor instructions in the instruction set causes the MC68020/EC020 to
initiate F-line emulator exception processing. If the F-line emulator exception is either of
these two situations, the main processor does not write to the control CIR prior to initiating
exception processing.
F-line exceptions can also occur if the operations requested by a coprocessor response
primitive are not compatible with the effective address type in bits 5–0 of the coprocessor
instruction operation word. The F-line emulator exceptions that can result from the use of
the M68000 coprocessor response primitives are summarized in Table 7-6. If the
exception is caused by receiving an invalid primitive, the main processor aborts the
coprocessor instruction in progress by writing an abort mask (refer to 7.3.2 Control CIR)
to the control CIR prior to F-line emulator exception processing.
Another type of F-line emulator exception occurs when a bus error occurs during the CIR
access that initiates a coprocessor instruction. The main processor assumes that the
coprocessor is not present and takes the exception.
When the main processor initiates F-line emulator exception processing, it uses the four-
word preinstruction exception stack frame (refer to Figure 7-41) and the F-line emulator
exception vector number 11. Thus, if the exception handler does not modify the stack
frame, the main processor attempts to restart the instruction that caused the exception
after it executes an RTE instruction to return from the exception handler.
If the cause of the F-line exception can be emulated in software, the handler stores the
results of the emulation in the appropriate registers of the programming model and in the
status register field of the saved stack frame. The exception handler adjusts the program
MOTOROLA
M68020 USER’S MANUAL
7- 55
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