MC68340PV16VE Freescale Semiconductor, MC68340PV16VE Datasheet - Page 158

• Manufacturer Part Number: MC68340PV16VE
• Description: IC MCU 32BIT 16MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68340PV16VE

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

5.3.3.2 DATA MOVEMENT INSTRUCTIONS. The MOVE instruction is the basic means of
transferring and storing address and data. MOVE instructions transfer byte, word, and
long-word operands from memory to memory, memory to register, register to memory,
and register to register. Address movement instructions (MOVE or MOVEA) transfer word
and long-word operands and ensure that only valid address manipulations are executed.
In addition to the general MOVE instructions, there are several special data movement
instructions—move multiple registers (MOVEM), move peripheral data (MOVEP), move
quick (MOVEQ), exchange registers (EXG), load effective address (LEA), push effective
address (PEA), link stack (LINK), and unlink stack (UNLK). Table 5-4 is a summary of the
data movement operations.
MOTOROLA
ROR
ROR (r = 0)
NOTE : The following notations apply to this table only.
Instruction
— =
U
?
X
N
Z
V
MOVEA
MOVEM
MOVEP
MOVEQ
MOVE
UNLK
EXG
LINK
LEA
PEA
Operations
=
=
=
=
=
=
=
Not affected
Undefined
See special definition
General case
C
Rm
Rm
Boolean AND
Boolean OR
Table 5-3. Condition Code Computations (Continued)
...
Dn, (d 16 , An)
(d 16 , An), Dn
# data Dn
Operand
R0
An, # d
ea , ea
list, ea
Syntax
Rn, Rn
ea , An
ea , An
ea , list
Freescale Semiconductor, Inc.
An
ea
Table 5-4. Data Movement Operations
For More Information On This Product,
—
—
X
N
Operand Size
MC68340 USER’S MANUAL
Go to: www.freescale.com
16, 32
16, 32
8, 16, 32
8
16, 32
16, 32
16, 32
Z
32
32
32
32
32
32
32
V
0
0
Rn
SP – 4
Source
Source
Listed registers
Source
Dn [31:24]
(An + d)
Immediate Data
SP – 4
An
ea
C
?
0
Dn [15:8]
(An + d + 4)
Rn
SP; (SP)
C = Dr – 1
An
SP; ea
Sm
Dm
Rm
R
n
r
LB
UB
Rm
SP, An
Destination
Destination
Listed registers
Dn [31:24]; (An + d + 2)
(An + d); Dn [23:16]
(An + d + 4); Dn [7:0]
=
=
=
=
=
=
=
=
=
Dn [15:8]; (An + d + 6)
An, SP + 4
Destination
Destination
Special Definition
(SP); SP
Source operand MSB
Destination operand MSB
Result operand MSB
Register tested
Bit Number
Shift count
Lower bound
Upper bound
NOT Rm
Operation
SP
SP
An, SP + d
(An + d + 2);
Dn [23:16];
(An + d + 6)
Dn [7:0]
SP
5- 21