MC68HC000EI8 Freescale Semiconductor, MC68HC000EI8 Datasheet - Page 88
MC68HC000EI8
Manufacturer Part Number
MC68HC000EI8
Description
IC MPU 16BIT 8MHZ 68-PLCC
Manufacturer
Freescale Semiconductor
Specifications of MC68HC000EI8
Processor Type
M680x0 32-Bit
Speed
8MHz
Voltage
3.3V, 5V
Mounting Type
Surface Mount
Package / Case
68-PLCC
Family Name
M68000
Device Core
ColdFire
Device Core Size
16/32Bit
Frequency (max)
8MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Supply Voltage (max)
5.25V
Operating Supply Voltage (min)
4.75V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
68
Package Type
PLCC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
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Quantity
Price
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supervisor mode. Therefore, when instruction execution resumes at the address specified
to process the exception, the processor is in the supervisor privilege mode.
The MOVE to SR, ANDI to SR, and EORI to SR instructions fetch all operands in the
supervisor mode, perform the appropriate update to the status register, and then fetch the
next instruction at the next sequential program counter address in the privilege mode
determined by the new S bit.
6.1.4 Reference Classification
When the processor makes a reference, it classifies the reference according to the
encoding of the three function code output lines. This classification allows external
translation of addresses, control of access, and differentiation of special processor states,
such as CPU space (used by interrupt acknowledge cycles). Table 6-1 lists the
classification of references.
MOTOROLA
The transition from supervisor to user mode can be
accomplished by any of four instructions: return from exception
(RTE) (MC68010 only), move to status register (MOVE to SR),
AND immediate to status register (ANDI to SR), and exclusive
OR immediate to status register (EORI to SR). The RTE
instruction in the MC68010 fetches the new status register and
program counter from the supervisor stack and loads each into
its respective register. Next, it begins the instruction fetch at
the new program counter address in the privilege mode
determined by the S bit of the new contents of the status
register.
M68000 8-/16-/32-BIT MICROPROCESSORS USER’S MANUAL
*Address space 3 is reserved for user definition, while 0 and
4 are reserved for future use by Motorola.
Freescale Semiconductor, Inc.
FC2
Function Code Output
0
0
0
0
1
1
1
1
For More Information On This Product,
Table 6-1. Reference Classification
FC1
0
0
1
1
0
0
1
1
Go to: www.freescale.com
FC0
0
1
0
1
0
1
0
1
NOTE
(Undefined, Reserved)*
(Undefined, Reserved)*
(Undefined, Reserved)*
Supervisor Program
Address Space
Supervisor Data
User Program
CPU Space
User Data
6- 3