MMA8210EGR2 Freescale Semiconductor, MMA8210EGR2 Datasheet - Page 6
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MMA8210EGR2
Manufacturer Part Number
MMA8210EGR2
Description
Board Mount Accelerometers X- AXIS 100G SOIC 16
Manufacturer
Freescale Semiconductor
Series
MMA82r
Datasheet
1.MMA8104EGR2.pdf
(47 pages)
Specifications of MMA8210EGR2
Sensing Axis
X
Acceleration
100 g
Sensitivity
4.01 mV/g
Package / Case
SOIC-16
Axis
X or Y
Acceleration Range
±100g
Voltage - Supply
6.3 V ~ 30 V
Output Type
Digital
Bandwidth
-
Interface
SPI
Mounting Type
Surface Mount
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
1.3.6
The output of the sensor interface circuitry can be monitored at the C
between external signals and the input to the A/D converter. If C
input impedance located as close to this pin as possible are required. The circuit configuration shown in
recommended.
This pin may be configured as an input to the A/D converter when the MMA81XXEG, MMA82XXEG and MMA82XXTEG devices
are in test mode. Refer to
1.3.7
These pins are used for programming the device during manufacturing. These pins have internal pull-up or pull-down devices to
drive the input when left unconnected. The following termination is recommended for these pins in the end application:
CLK may be connected to ground, however this is not advised if the GLDE bit in DEVCFG2 is set, as a short between the adjacent
V
1.3.8
V
supplies a constant current through V
D
pull-down device and must be connected as shown in
Ground loss detection circuitry is enabled when the GLDE bit is programmed to a logic ‘1’ state in DEVCFG2. Ground loss
detection is not available when the master operates in differential mode. V
DSI bus is configured for differential operation. V
When ground loss detection is enabled, a constant current is sourced and the voltage at V
open connection between V
between chassis ground and V
detection threshold. Should the counter overflow, a ground loss condition is indicated. The counter acts as a digital low-pass filter,
to provide immunity from spurious signals.
This pin functions as the SPI data input when the device is in test mode.
MMA81XXEG
6
GND
GND
IN
and the system’s virtual ground. A fault condition is signalled if the resistance exceeds specified limits. This pin has no internal
/D
/D
IN
IN
pin and ground prevents ground loss detection.
may be used to detect an open condition between the satellite module and chassis. The ground loss detector circuit
C
Trim/Test Pins (V
GND Detect Pin (V
FIL
MMA81XXEG/MMA82XXEG//MMA82XXTEG
Appendix A
SS
SS
and chassis ground will cause the voltage to rise. If the voltage indicates that the connection
PP
GND
has opened, a 14-bit counter is enabled. This counter will reverse if the voltage falls below the
/TEST, CLK, DOUT)
/D
GND
Figure 1-4. C
for further details regarding test mode operation.
IN
/D
)
IN
and measures resulting voltage. This determines the resistance between V
V
GND
PP
C
D
CLK
PIN
/TEST
OUT
FIL
FIL
/D
Figure
IN
Filter and Buffer Configuration
5
connection options are illustrated in
Table 1-1
1-5.
FIL
Leave unconnected
Leave unconnected
Connect to ground
50 kΩ
monitoring is desired, a low-pass filter and a buffer with high
Termination
FIL
pin. An internal buffer is provided to provide isolation
GND
680 pF
/D
IN
must be directly connected to BUSRTN if the
RIN ≥ 1 MΩ
GND
Figure
is continuously monitored. An
1-5.
Freescale Semiconductor
Figure 1-5
is
Sensors
GND
/