MC8640DTHX1067NC Freescale Semiconductor, MC8640DTHX1067NC Datasheet - Page 65

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MC8640DTHX1067NC

Manufacturer Part Number
MC8640DTHX1067NC
Description
MPU DUAL E600 1023-FCCBGA
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MC8640DTHX1067NC

Processor Type
MPC86xx PowerPC 32-Bit
Speed
1.067GHz
Voltage
0.95V
Mounting Type
Surface Mount
Package / Case
1023-FCCBGA
Family Name
MC8xxx
Device Core
PowerQUICC
Device Core Size
32b
Frequency (max)
1.067GHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
0.95/1.05V
Operating Supply Voltage (max)
1/1.1V
Operating Supply Voltage (min)
0.9/1V
Operating Temp Range
-40C to 105C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
1023
Package Type
FCCBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Lead Free Status / Rohs Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC8640DTHX1067NC
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Please consult with the clock driver chip manufacturer to verify whether this connection scheme is
compatible with a particular clock driver chip.
Figure 46
It assumes the DC levels of the clock driver are compatible with MPC8640D SerDes reference clock
input’s DC requirement.
13.2.4
The clock driver selected should provide a high quality reference clock with low phase noise and
cycle-to-cycle jitter. Phase noise less than 100 kHz can be tracked by the PLL and data recovery loops and
is less of a problem. Phase noise above 15 MHz is filtered by the PLL. The most problematic phase noise
Freescale Semiconductor
Single-Ended
CLK Driver Chip
Clock Driver
LVPECL CLK
Driver Chip
Clock Driver
Clock Driver
Figure 45. AC-Coupled Differential Connection with LVPECL Clock Driver (Reference Only)
shows the SerDes reference clock connection reference circuits for a single-ended clock driver.
AC Requirements for SerDes Reference Clocks
CLK_Out
CLK_Out
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3
CLK_Out
Figure 46. Single-Ended Connection (Reference Only)
33 Ω
R1
R1
100 Ω differential PWB trace
Total 50 Ω. Assume clock driver’s
output impedance is about 16 Ω.
R2
R2
50 Ω
100 Ω differential PWB trace
10nF
10nF
10nF
SD n _REF_CLK
SD n _REF_CLK
SD n _REF_CLK
SD n _REF_CLK
50 Ω
50 Ω
High-Speed Serial Interfaces (HSSI)
50 Ω
50 Ω
MPC8640D
MPC8640D
SerDes Refer.
CLK Receiver
SerDes Refer.
CLK Receiver
65

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