ATF22LV10C-10SC Atmel, ATF22LV10C-10SC Datasheet - Page 7
![IC PLD EE 10NS 24-SOIC](/photos/6/70/67046/453-24-soic_sml.jpg)
ATF22LV10C-10SC
Manufacturer Part Number
ATF22LV10C-10SC
Description
IC PLD EE 10NS 24-SOIC
Manufacturer
Atmel
Datasheet
1.ATF22LV10C-10XU.pdf
(19 pages)
Specifications of ATF22LV10C-10SC
Programmable Type
EE PLD
Number Of Macrocells
10
Voltage - Input
3.3V
Speed
10ns
Mounting Type
Surface Mount
Package / Case
24-SOIC (7.5mm Width)
Family Name
ATF22LV10C
Process Technology
CMOS
# Macrocells
10
# I/os (max)
10
Frequency (max)
83.3MHz
Propagation Delay Time
10ns
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
5.5V
Supply Current
85mA
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
24
Package Type
SOIC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
0780M–PLD–7/10
8.
Power-down Mode
The Atmel
PD pin acts as the power-down pin (Pin 4 on the DIP/SOIC packages and Pin 5 on the PLCC package). When the
PD pin is high, the device supply current is reduced to less than 100mA. During power-down, all output data and
internal logic states are latched and held. Therefore, all registered and combinatorial output data remain valid. Any
outputs which were in an undetermined state at the onset of power-down will remain at the same state. During
power-down, all input signals except the power-down pin are blocked. Input and I/O hold latches remain active to
insure that pins do not float to indeterminate levels, further reducing system power. The power-down pin feature is
enabled in the logic design file. Designs using the power-down pin may not use the PD pin logic array input.
However, all other PD pin macrocell resources may still be used, including the buried feedback and foldback
product term array inputs.
PD pin configuration is controlled by the design file, and appears as a separate fuse bit in the JEDEC file. When
the power-down feature is not specified in the design file, the IN/PD pin will be configured as a regular logic input.
Note:
Figure 8-1.
Figure 8-2.
INPUT
DATA
OE
Some programmers list the 22V10 JEDEC-compatible 22V10C (no PD used) separately from the non-22V10 JEDEC-
compatible 22V10CEX (with PD used).
INPUT
®
ATF22LV10C includes an optional pin controlled power-down feature. When this mode is enabled, the
Input Diagram
I/O Diagram
V
V
CC
CC
PROTECTION
100K
CIRCUIT
ESD
I/O
100K
V
CC
Atmel ATF22LV10C
7