ATF22LV10C-15JI Atmel, ATF22LV10C-15JI Datasheet - Page 7

• Manufacturer Part Number: ATF22LV10C-15JI
• Description: IC PLD 15NS 28PLCC
• Manufacturer: Atmel

Specifications of ATF22LV10C-15JI

• Programmable Type: EE PLD
• Number Of Macrocells: 10
• Voltage - Input: 3.3V
• Speed: 15ns
• Mounting Type: Surface Mount
• Package / Case: 28-PLCC
• Family Name: ATF22LV10C
• Process Technology: CMOS
• # Macrocells: 10
• # I/os (max): 10
• Frequency (max): 62.5MHz
• Propagation Delay Time: 15ns
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 5.5V
• Supply Current: 90mA
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 28
• Package Type: PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: ATF22LV10C15JI

0780M–PLD–7/10
8.
Power-down Mode
The Atmel
PD pin acts as the power-down pin (Pin 4 on the DIP/SOIC packages and Pin 5 on the PLCC package). When the
PD pin is high, the device supply current is reduced to less than 100mA. During power-down, all output data and
internal logic states are latched and held. Therefore, all registered and combinatorial output data remain valid. Any
outputs which were in an undetermined state at the onset of power-down will remain at the same state. During
power-down, all input signals except the power-down pin are blocked. Input and I/O hold latches remain active to
insure that pins do not float to indeterminate levels, further reducing system power. The power-down pin feature is
enabled in the logic design file. Designs using the power-down pin may not use the PD pin logic array input.
However, all other PD pin macrocell resources may still be used, including the buried feedback and foldback
product term array inputs.
PD pin configuration is controlled by the design file, and appears as a separate fuse bit in the JEDEC file. When
the power-down feature is not specified in the design file, the IN/PD pin will be configured as a regular logic input.
Note:
Figure 8-1.
Figure 8-2.
INPUT
DATA
OE
Some programmers list the 22V10 JEDEC-compatible 22V10C (no PD used) separately from the non-22V10 JEDEC-
compatible 22V10CEX (with PD used).
INPUT
®
ATF22LV10C includes an optional pin controlled power-down feature. When this mode is enabled, the
Input Diagram
I/O Diagram
V
V
CC
CC
PROTECTION
100K
CIRCUIT
ESD
I/O
100K
V
CC
Atmel ATF22LV10C
7