CY7C342B-25JC Cypress Semiconductor Corp, CY7C342B-25JC Datasheet
CY7C342B-25JC
Specifications of CY7C342B-25JC
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CY7C342B-25JC Summary of contents
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... LAB. Each LAB is interconnected with a programmable interconnect array, allowing all signals to be routed throughout the chip. The speed and density of the CY7C342B allows used in a wide range of applications, from replacement of large amounts of 7400-series TTL logic, to complex controllers and multifunction chips. With greater than 25 times the functionality of 20-pin PLDs, the CY7C342B allows the replacement of over 50 TTL devices ...
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... E I/O GND I/O 49 I/O 48 I/O I/O I I I/O I/O I I/O I CY7C342B 7C342B-30 7C342B- PGA Bottom View I/O INPUT INPUT INPUT I/O I/O I/O I/O I/O GND INPUT V I/O I/O CC 7C342B INPUT/ I/O I/O V GND I/O I/O CC CLK ...
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... Logic Array Blocks There are eight logic array blocks in the CY7C342B. Each LAB consists of a macrocell array containing 16 macrocells, an expander product term array containing 32 expanders, and an I/O block. The LAB is fed by the programmable interconnect array and the dedicated input bus. All macrocell feedbacks go to the macrocell array, the expander array, and the program- mable interconnect array ...
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... The bit that controls this function, along with all other program data, may be reset simply by erasing the entire device. The CY7C342B is fully functionally tested and guaranteed through complete testing of each programmable EPROM bit and all internal logic elements thus ensuring 100% programming yield ...
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... CC Test Conditions 1.0 MHz 0V 1.0 MHz OUT R1 464 250 INCLUDING JIG AND SCOPE (b) 1.75V parameter refers to low-level TTL output current. OL CY7C342B [1] ................... – +25 mA [1] .........................................–2.0V to +7.0V Ambient Temperature +70 C – +85 C Min. Max. 4.75(4.5) 5.25(5.5) 2.4 0.45 2 0.3 CC –0.3 0.8 –10 +10 – ...
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... This parameter is measured with a 16-bit counter programmed into each LAB 6. This parameter is measured with a positive-edge triggered clock at the register. For negative edge triggering, the t Document #: 38-03014 Rev. *A Description [3] [3] [3] [4] [5] Description [3] [3] [3] [4] [5] Description [3] [6] [6] [5] [3] CY7C342B Over Operating Range 7C342B-15 7C342B-20 Min. Max. Min. Max 100 71 ...
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... Flow Through Latch Delay LATCH t Register Delay RD Notes pF. 8. Sample tested only for an output change of 500 mV. Document #: 38-03014 Rev. *A Description [5] [5] [5] Description [3] [3] [7] [3] [3] [7] CY7C342B Over Operating Range (continued) 7C342B-15 7C342B–20 Min. Max. Min. Max. Unit 33.3 Over Operating Range 7C342B-15 7C342B-20 Min ...
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... This specification guarantees the maximum combinatorial delay associated with the macrocell register bypass when the macrocell is configured for combina- torial operation. Document #: 38-03014 Rev. *A Description t /t PD1 PD2 CO1 AS1 CY7C342B Over Operating Range (continued) 7C342B-25 7C342B-30 7C342B-35 Min. Max. Min. Max. Min ...
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... CLOCK INTO LOGIC ARRAY CLOCK FROM LOGIC ARRAY DATA FROM LOGIC ARRAY REGISTER OUTPUT TO LOCAL LAB LOGIC ARRAY REGISTER OUTPUT TO ANOTHER LAB Document #: 38-03014 Rev EXP AWL RSU LATCH FD t PIA CY7C342B LAC LAD t t COMB HIGH IMPEDANCE STATE CLR PRE FD Page ...
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... IN SYSTEM CLOCK AT REGISTER t RSU DATA FROM LOGIC ARRAY Ordering Information Speed (ns) Ordering Code 15 CY7C342B-15JC/JI 20 CY7C342B-20JC/JI 25 CY7C342B-25HC/HI CY7C342B-25JC/JI CY7C342B-25RC/RI 30 CY7C342B-30JC/JI 35 CY7C342B-35JC/JI CY7C342B-35RJ/RI Document #: 38-03014 Rev ICS t RH Package Name Package Type J81 68-lead Plastic Leaded Chip Carrier J81 68-lead Plastic Leaded Chip Carrier ...
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... Package Diagrams Document #: 38-03014 Rev. *A 68-pin Windowed Leaded Chip Carrier H81 CY7C342B 51-80080 Page ...
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... Package Diagrams (continued) Document #: 38-03014 Rev. *A 68-lead Plastic Leaded Chip Carrier J81 CY7C342B 51-85005-A Page ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 68-Pin Windowed PGA Ceramic R68 CY7C342B 51-80099-*A Page ...
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... Document Title: CY7C342B 128-Macrocell MAX Document Number: 38-03014 Issue REV. ECN NO. Date ** 106314 04/25/01 *A 113612 04/11/02 Document #: 38-03014 Rev. *A ® EPLD Orig. of Change SZV Change from Spec number: 38-00119 to 38-03014 OOR PGA package diagram dimensions were updated CY7C342B Description of Change Page ...