CS4265-CNZ Cirrus Logic Inc, CS4265-CNZ Datasheet - Page 24

• Manufacturer Part Number: CS4265-CNZ
• Description: IC CODEC 24BIT 104DB 32QFN
• Manufacturer: Cirrus Logic Inc
• Type: Stereo Audior

Specifications of CS4265-CNZ

• Package / Case: 32-QFN
• Data Interface: PCM Audio Interface
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 104 / 104
• Voltage - Supply, Analog: 3.13 V ~ 5.25 V
• Voltage - Supply, Digital: 3.13 V ~ 5.25 V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 4
• Number Of Dac Outputs: 2
• Conversion Rate: 192 KSPS
• Interface Type: Serial (I2S)
• Resolution: 24 bit
• Operating Supply Voltage: 3.3 V, 5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 10 C
• Number Of Channels: 2 ADC/2 DAC
• Thd Plus Noise: - 95 dB ADC / - 90 dB DAC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1001 - BOARD EVAL FOR CS4265 CODEC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1039

24
4. APPLICATIONS
4.1
4.2
4.2.1
LRCK
Mode
(kHz)
176.4
44.1
88.2
128
192
32
48
64
96
Recommended Power-Up Sequence
1. Hold RESET low until the power supply,MCLK, and LRCK are stable. In this state, the Control Port is
2. Bring RESET high. The device will remain in a low power state with the PDN bit set by default. The con-
3. The desired register settings can be loaded while the PDN bit remains set.
4. Clear the PDN bit to initiate the power-up sequence.
System Clocking
The CS4265 will operate at sampling frequencies from 4 kHz to 200 kHz. This range is divided into three
speed modes as shown in
Master Clock
MCLK/LRCK must maintain an integer ratio as shown in
frequency at which audio samples for each channel are clocked into or out of the device. The FM bits (See
“Functional Mode (Bits 7:6)” on page
on page
clocks in Slave Mode.
LRCK frequencies.
11.2896
12.2880
8.1920
reset to its default settings.
trol port will be accessible.
64x
-
-
-
-
-
-
38.) configure the device to generate the proper clocks in Master Mode and receive the proper
12.2880
16.9344
18.4320
96x
-
-
-
-
-
-
Table 2
Single-Speed
Double-Speed
Quad-Speed
11.2896
12.2880
16.3840
22.5792
24.5760
Table
8.1920
128x
QSM
-
-
-
Table 2. Common Clock Frequencies
illustrates several standard audio sample rates and the required MCLK and
1.
Mode
12.2880
16.9344
18.4320
24.5760
33.8680
36.8640
Table 1. Speed Modes
37.) and the MCLK Freq bits (See
192x
-
-
-
MCLK (MHz)
Sampling Frequency
12.2880
16.3840
22.5792
24.5760
32.7680
45.1584
49.1520
11.2896
8.1920
256x
100-200 kHz
50-100 kHz
4-50 kHz
Table
12.2880
16.9344
18.4320
24.5760
33.8680
36.8640
384x
2. The LRCK frequency is equal to Fs, the
-
-
-
DSM
“MCLK Frequency - Address 05h”
16.3840
22.5792
24.5760
32.7680
45.1584
49.1520
512x
-
-
-
24.5760
33.8680
36.8640
768x
-
-
-
-
-
-
SSM
CS4265
32.7680
45.1584
49.1520
DS657F2
1024x
-
-
-
-
-
-