CS4245-CQZ Cirrus Logic Inc, CS4245-CQZ Datasheet

IC CODEC AUD STER 104DB 48LQFP

CS4245-CQZ

Manufacturer Part Number
CS4245-CQZ
Description
IC CODEC AUD STER 104DB 48LQFP
Manufacturer
Cirrus Logic Inc
Type
Stereo Audior
Datasheet

Specifications of CS4245-CQZ

Package / Case
48-LQFP
Data Interface
Serial
Resolution (bits)
24 b
Number Of Adcs / Dacs
2 / 2
Sigma Delta
Yes
Dynamic Range, Adcs / Dacs (db) Typ
104 / 104
Voltage - Supply, Analog
3.13 V ~ 5.25 V
Voltage - Supply, Digital
3.13 V ~ 5.25 V
Operating Temperature
-10°C ~ 70°C
Mounting Type
Surface Mount
Number Of Adc Inputs
12
Number Of Dac Outputs
4
Conversion Rate
192 KSPS
Interface Type
Serial (I2C, SPI)
Resolution
24 bit
Operating Supply Voltage
3.3 V, 5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 10 C
Number Of Channels
2 ADC/2 DAC
Thd Plus Noise
- 95 dB ADC / - 90 dB DAC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1501 - BOARD EVAL FOR CS4245 CODEC
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
598-1034

Available stocks

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Part Number:
CS4245-CQZ
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CIRRUS
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CS4245-CQZ
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
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CS4245-CQZ
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Part Number:
CS4245-CQZR
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Quantity:
1 000
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CS4245-CQZR
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Cirrus Logic Inc
Quantity:
10 000
D/A Features
ADC Overflow
Control Data
Multi-bit Delta Sigma Modulator
104 dB Dynamic Range
-90 dB THD+N
Up to 192 kHz Sampling Rates
Single-Ended Analog Architecture
Volume Control with Soft Ramp
Popguard
Filtered Line-Level Outputs
Selectable Serial Audio Interface Formats
Selectable 50/15 µs De-Emphasis
Control Output for External Muting
http://www.cirrus.com
Interrupt
I
Output
2
Reset
Serial
Audio
C/SPI
Serial
Audio
Input
0.5 dB Step Size
Zero Crossing, Click-Free Transitions
Minimizes the Effects of Output Transients
Left-Justified up to 24-bit
I²S up to 24-bit
Right-Justified 16-, 18-, 20-, and 24-bit
104 dB, 24-Bit, 192 kHz Stereo Audio CODEC
1.8 V to 5 V
®
Technology
High Pass
High Pass
Volume
Control
Volume
Control
Filter
Filter
Register Configuration
3.3 V to 5 V
Interpolation
Interpolation
Anti-Alias Filter
Anti-Alias Filter
Filter
Filter
Low-Latency
Low-Latency
Copyright © Cirrus Logic, Inc. 2007
(All Rights Reserved)
ΔΣ Modulator
ΔΣ Modulator
Multibit
Multibit
A/D Features
Internal Voltage
Oversampling
Oversampling
Reference
Multi-bit Delta Sigma Modulator
104 dB Dynamic Range
-95 dB THD+N
Stereo 6:1 Input Multiplexer
Programmable Gain Amplifier (PGA)
Stereo Microphone Inputs
Up to 192 kHz Sampling Rates
Selectable Serial Audio Interface Formats
High-Pass Filter or DC Offset Calibration
Multibit
Multibit
ADC
ADC
± 12 dB Gain, 0.5 dB Step Size
Zero Crossing, Click-Free Transitions
+32 dB Gain Stage
Low-Noise Bias Supply
Left-Justified up to 24-bit
I²S up to 24-bit
Switched Capacitor
Switched Capacitor
DAC and Filter
DAC and Filter
3.3 V to 5 V
PGA
PGA
MUX
Control
Mute
MUX
+32 dB
+32 dB
CS4245
Left DAC Output
Mute Control
Right DAC Output
Left Aux Output
Right Aux Output
Stereo Input 1
Stereo Input 2
Stereo Input 3
Stereo Input 4 /
Mic Input 1 & 2
Stereo Input 5
Stereo Input 6
AUGUST '07
DS656F2

Related parts for CS4245-CQZ

CS4245-CQZ Summary of contents

Page 1

... ADC Multibit Low-Latency Oversampling Filter Anti-Alias Filter ADC Copyright © Cirrus Logic, Inc. 2007 (All Rights Reserved) CS4245 ± Gain, 0.5 dB Step Size Zero Crossing, Click-Free Transitions +32 dB Gain Stage Low-Noise Bias Supply Left-Justified up to 24-bit I² 24-bit 3 Switched Capacitor DAC and Filter ...

Page 2

... Integrated level translators allow easy interfacing be- tween the CS4245 and other devices operating over a wide range of logic levels. The CS4245 is available in a 48-pin LQFP package in both Commercial (-10° to +70° C) and Automotive (-40° to +105° C) grade. The CDB4245 Customer Demon- stration board is also available for device evaluation and implementation suggestions. Please see formation” ...

Page 3

... Synchronization of Multiple Devices ............................................................................................. 38 4.16 Grounding and Power Supply Decoupling .................................................................................... 38 5. REGISTER QUICK REFERENCE ........................................................................................................ 39 6. REGISTER DESCRIPTION .................................................................................................................. 40 6.1 Chip ID - Register 01h .................................................................................................................... 40 6.2 Power Control - Address 02h ......................................................................................................... 40 6.2.1 Freeze (Bit 7) ......................................................................................................................... 40 6.2.2 Power-Down MIC (Bit 3) ........................................................................................................ 40 6.2.3 Power-Down ADC (Bit 2) ....................................................................................................... 40 DS656F2 ........................................................................................................................ 6 CS4245 3 ...

Page 4

... Interrupt Mode MSB - Address 0Fh .............................................................................................. 49 6.16 Interrupt Mode LSB - Address 10h ............................................................................................... 49 7. PARAMETER DEFINITIONS ................................................................................................................ 50 8. DAC FILTER PLOTS 9. ADC FILTER PLOTS 10. PACKAGE DIMENSIONS .................................................................................................................. 55 11. THERMAL CHARACTERISTICS AND SPECIFICATIONS ............................................................. 55 12. ORDERING INFORMATION 13. REVISION HISTORY .......................................................................................................................... 56 LIST OF FIGURES Figure 1.DAC Output Test Load ................................................................................................................ 11 4 .................................................................................................................... 51 ......................................................................................................................... 53 ..................................................................................................... 56 CS4245 DS656F2 ...

Page 5

... Figure 43.ADC Quad-Speed Transition Band (Detail) .............................................................................. 54 Figure 44.ADC Quad-Speed Passband Ripple ......................................................................................... 54 LIST OF TABLES Table 1. Speed Modes .............................................................................................................................. 29 Table 2. Common Clock Frequencies ....................................................................................................... 30 Table 3. Slave Mode Serial Bit Clock Ratios ............................................................................................. 31 Table 4. Device Revision .......................................................................................................................... 40 Table 5. Freeze-able Bits .......................................................................................................................... 40 Table 6. Functional Mode Selection ......................................................................................................... 41 Table 7. DAC Digital Interface Formats .................................................................................................... 41 DS656F2 CS4245 5 ...

Page 6

... Table 13. Auxiliary Output Source Selection ............................................................................................. 44 Table 14. Example Gain and Attenuation Settings ................................................................................... 45 Table 15. PGA Soft Cross or Zero Cross Mode Selection ........................................................................ 46 Table 16. Analog Input Multiplexer Selection ............................................................................................ 46 Table 17. Digital Volume Control Example Settings ................................................................................. 47 Table 18. DAC Soft Cross or Zero Cross Mode Selection ........................................................................ 47 6 CS4245 DS656F2 ...

Page 7

... Stereo Analog Input 2 (Input) - The full-scale level is specified in the ADC Analog Characteristics 9, 10 AIN2B specification table. AIN1A Stereo Analog Input 1 (Input) - The full-scale level is specified in the ADC Analog Characteristics 11, 12 AIN1B specification table. DS656F2 CS4245 CS4245 VLS 36 35 MUTEC 34 AOUTB 33 AOUTA 32 AGND 31 AGND ...

Page 8

... Digital Ground (Input) - Ground reference for the internal digital section Digital Power (Input) - Positive power for the internal digital section. INT 47 Interrupt (Output) - Indicates an interrupt condition has occurred. OVFL 48 ADC Overflow (Output) - Indicates an ADC overflow condition is present. 8 “Auxiliary Output Source Select (Bits 6:5)” on page CS4245 45. DS656F2 ...

Page 9

... Analog VA Digital VD Logic - Serial Port VLS Logic - Control Port VLC (Note AGND-0.3 INA V Logic - Serial Port IND-S Logic - Control Port V IND stg CS4245 Nom Max Units 5.0 5.25 V 3.3 (Note 1) V 3.3 5.25 V 3.3 5.25 V °C - +70 - +105 °C Min Max Units -0 ...

Page 10

... THD -90 - -70 - -30 (1 kHz) - 100 - 0.1 - 100 0.60*VA 0.65*VA 0.70*VA 0.60*VA 0.65*VA 0.70*VA (Note OUT (Note (Note 150 OUT CS4245 = 3 kΩ (see L L Automotive Grade Max Min Typ Max - 96 104 - - 93 101 - - -84 - - -41 - -87 - - 101 - - 90 ...

Page 11

... L Symbol to -0.1 dB corner corner -0.175 0.5465 (Note 8) tgd Fs = 44.1 kHz to -0.1 dB corner corner 0.5770 (Note 8) tgd to -0.1 dB corner corner (Note 8) tgd CS4245 affects the dominant pole of the L Min Typ Max Unit Single-Speed Mode 0.4992 - +0. ...

Page 12

... AOUTx R L AGND Figure 1. DAC Output Test Load 12 125 100 V 75 out 2 Figure 2. Maximum DAC Loading CS4245 Safe Operating Region Resistive Load -- R (k Ω DS656F2 ...

Page 13

... Line-Level Inputs Commercial Grade Symbol Min Typ 98 104 95 101 - (Note 12 -95 - - -92 THD -92 - -75 - - 101 (Note 12 -92 - - THD -89 - - -81 CS4245 = -10° to +70° C for Commercial or -40° to Figure 12 on page 29. Automotive Grade Max Min Typ Max - 96 104 - - 93 101 - - - -89 - - -92 - -86 - - 101 - - ...

Page 14

... Symbol Min Typ - ± - 100 0.51*VA 0.57*VA 0.63*VA 0.51*VA 0.57*VA 0.63*VA (Note 11) 6.12 6 Line-Level and Microphone-Level Inputs Commercial Grade Symbol Min Typ - 0 CS4245 Automotive Grade Max Min Typ Max Unit - - 90 - ± 10 ± ± 100 - ppm/°C 7.48 5.44 6.8 8.16 ...

Page 15

... Valid for Double- and Quad-Speed Modes only. 14. Valid when the microphone-level inputs are selected. DS656F2 Microphone-Level Inputs Commercial Grade Symbol Min Typ -80 - -60 THD -80 - -60 THD ± ± - 300 0.013*VA 0.017*VA 0.021*VA 0.013*VA 0.017*VA 0.021* CS4245 Automotive Grade Max Min Typ Max - -74 - - -74 - -80 - -60 ...

Page 16

... Response is clock-dependent and will scale with Fs. Note that the response plots normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs. 16 Symbol Min Typ 0.5688 - 12/ 0.5604 - 9/ 0.5000 - 5/ (Note 16) 20 (Note 16 /Fs (Figures 33 CS4245 Max Unit 0.4896 Fs 0.035 0.4896 Fs 0.025 0.2604 Fs 0.025 Deg 44) are DS656F2 ...

Page 17

... THD -80 - - (Note 19 -74 -20 dB THD+N - - -68 (Notes 18) 98 104 95 101 -80 - -81 -60 dB THD -80 - -73 - -33 CS4245 = -10° to +70° C for Commercial or -40° to Figure 12 on page 29. Automotive Grade Max Min Typ Max - 96 104 - - 93 101 - - -74 - - -41 - -74 - - -68 - -74 -66 - ...

Page 18

... Referred to the typical Line-Level Full-Scale Input Voltage 3. 3.46 V Commercial Grade Symbol Min Typ 93 101 (Note 19 -80 - -78 -60 dB THD -80 - - (Note 19 -74 -20 dB THD+N - - -68 (Notes 18) 95 101 -80 - -78 -60 dB THD -80 - -70 - -30 CS4245 Automotive Grade Max Min Typ Max - 91 101 - - -74 - - -38 - -74 - - -68 - - 101 - - 90 98 ...

Page 19

... Commercial Grade Symbol Min Typ - 0.1 ± ± - 100 - 0.3 ± ± - 300 - 0.1 ± - 100 (Note 22) -0.1dB - (Note 21) - 180 OUT R 100 - CS4245 Automotive Grade Max Min Typ Max Unit - - 0 ± ± 100 - ppm/° 0 ± ± 300 - ppm/° 0.1 ...

Page 20

... Guaranteed by design. The DC current draw represents the allowed current draw due to typical leakage through the electrolytic de-coupling capacitors. 20 Symbol 3 VD, VLS, VLC = VD, VLS, VLC = 3 VLS, VLC, VD (Note 24) PSRR VQ1 (Note 25 VQ2 (Note 25 FILT1+ FILT2+ MICBIAS I MB CS4245 Min Typ Max - 0. 0. 400 485 - 198 241 - 4 0 ...

Page 21

... Serial Port V 0.8xVLS IH Control Port V 0.8xVLC IH Serial Port V 0.7xVLS IH Control Port V 0.7xVLC IH Serial Port Control Port Serial Port V VLS-1.0 OH Control Port V VLC-1.0 OH MUTEC V VA-1.0 OH Serial Port Control Port MUTEC (Note 27 ------------------- - LRCK1 CS4245 Typ Max Units - - 0.2xVLS V - 0.2xVLC ±10 μ μ ...

Page 22

... Single Speed Mode Fs Double Speed Mode Fs Quad Speed Mode Fs f 1.024 mclk t clkhl t slr t sdo Single-Speed Mode t -------------------- - sclkw ( 128 Double-Speed Mode t ----------------- - sclkw ( 64 Quad-Speed Mode t ----------------- - sclkw ( 64 t sclkh t sclkl t slr t sdo 23. CS4245 Min Typ Max Unit kHz 50 - 100 kHz 100 - 200 kHz - 51.200 MHz - ...

Page 23

... LRCK1 Output SCLK1 Output SDOUT Figure 3. Master Mode Timing - Serial Audio Port 1 LRCK1 Input SCLK1 Input SDOUT Figure 4. Slave Mode Timing - Serial Audio Port 1 DS656F2 t slr t sdo t t sclkh slr t sclkw t sdo CS4245 t sclkl 23 ...

Page 24

... Double Speed Mode Fs Quad Speed Mode Fs f 1.024 mclk t clkhl t slr t sdis t sdih Single-Speed Mode t -------------------- - sclkw ( 128 Double-Speed Mode t ----------------- - sclkw ( 64 Quad-Speed Mode t ----------------- - sclkw ( 64 t sclkh t sclkl t slr t sdis t sdih 25. CS4245 Min Typ Max Unit kHz 50 - 100 kHz 100 - 200 kHz - 51.200 MHz - ...

Page 25

... LRCK2 Output SCLK2 Output SDIN Figure 5. Master Mode Timing - Serial Audio Port 2 LRCK2 Input SCLK2 Input SDIN Figure 6. Slave Mode Timing - Serial Audio Port 2 DS656F2 t slr t sdis t t sclkh slr t sclkw t sdis CS4245 t sdih t sclkl t sdih 25 ...

Page 26

... MSB - LRCK Channel A - Left SCLK SDATA LSB MSB - LSB MSB + LSB MSB Figure 8. Format 1, I² 24-Bit Data - LSB Figure 9. Format 2, Right-Justified 16-Bit Data. Format 3, Right-Justified 24-Bit Data. CS4245 Channel B - Right - LSB Channel B - Right + LSB Channel B - Right MSB - LSB DS656F2 ...

Page 27

... Figure 10. Control Port Timing - I²C Format CS4245 Min Max - 100 500 - 4.7 - 4.0 - 4.7 - 4 250 - - 300 fd 4.7 - 300 1000 , of SCL ate d Sta rt ...

Page 28

... CS t css CCLK CDIN CDOUT pF. L Symbol f sck t srs t csh t css t scl t sch t dsu (Note 32 (Note 33 (Note 33 srs t scl t sch dsu Figure 11. Control Port Timing - SPI Format CS4245 Min Max Units - 6.0 MHz 500 - ns 1.0 - μ 100 ns - 100 ns t csh DS656F2 ...

Page 29

... Fs R 470 ext This circuitry is intended for applications where the CS4245 connects directly to an unbalanced output of the design . For internal routing applications please see the DAC Analog Output Characteristics section for loading limitations . 10 µF 0.1 µF 47 µF 0.1 µF 47 µF 0.1 µ ...

Page 30

... Clear the PDN bit to initiate the power-up sequence. 4.2 System Clocking The CS4245 will operate at sampling frequencies from 4 kHz to 200 kHz. This range is divided into three speed modes as shown in The CS4245 has two serial ports which may be operated synchronously or asynchronously. Serial port 1 consists of the SCLK1 and LRCK1 signals and clocks the serial audio output, SDOUT ...

Page 31

... DAC_FM Bits ÷2 010 1 ÷4 ÷3 011 ÷2 ÷4 100 ÷1 Figure 13. Master Mode Clocking CS4245 Table 2 illustrates several standard audio 384x 512x 768x 12.2880 16.3840 24.5760 16.9344 22.5792 33.8680 18.4320 24.5760 36.8640 24.5760 32.7680 - 33.8680 45 ...

Page 32

... High-Pass Filter and DC Offset Calibration When using operational amplifiers in the input circuitry driving the CS4245, a small DC offset may be driven into the A/D converter. The CS4245 includes a high-pass filter after the decimator to remove any DC offset which could result in recording a DC level, possibly yielding clicks when switching between devices in a mul- tichannel system ...

Page 33

... The recommended external analog circuitry is shown in the Typical Connection Diagram. The CS4245 DAC does not include phase or amplitude compensation for an external filter. Therefore, the DAC system phase and amplitude response is dependent on the external analog circuitry. DS656F2 ...

Page 34

... For this reason, a high input impedance buffer must be used on the AUXOUT pins to achieve full performance. Refer to the table in ceptable loading conditions. 4.9 De-Emphasis Filter The CS4245 includes on-chip digital de-emphasis optimized for a sample rate of 44.1 kHz. The filter re- sponse is shown in Figure changes in sample rate, Fs. Please see phasis control. ...

Page 35

... Internal Digital Loopback The CS4245 supports an internal digital loopback mode in which the output of the ADC is routed to the input of the DAC. This mode may be activated by setting the LOOP bit in the Signal Selection register (See tion 6.6 “Signal Selection - Address 06h” on page ating at the same synchronous sample rate ...

Page 36

... The control port has two modes: SPI and I²C, with the CS4245 acting as a slave device. SPI Mode is se- lected if there is a high-to-low transition on the AD0/CS pin, after the RESET pin has been brought high. I²C Mode is selected by connecting the AD0/CS pin through a resistor to VLC or DGND, thereby permanently selecting the desired AD0 bit address state ...

Page 37

... SDA while the clock is high. A Stop condition is a rising transition while the clock is high. All other transitions of SDA occur while the clock is low. The first byte sent to the CS4245 after a Start condition consists of a 7-bit chip address field and a R/W bit (high for a read, low for a write). ...

Page 38

... The CS4245 also has a dedicated overflow output. The OVFL pin functions as active low open drain and has no active pull-up transistor, thereby requiring an external pull-up resistor. The OVFL pin outputs the ADCOverflow and ADCUnderflow conditions available in the Interrupt Status register ...

Page 39

... CS4245s in the system. If only one master clock source is needed, one solution is to place one CS4245 in Master Mode, and slave all of the other CS4245s to the one master. If multiple master clock sources are needed, a possible solution would be to supply all clocks from the same external source and time the CS4245 reset with the inactive edge of master clock ...

Page 40

... Gain5 Gain4 Gain3 Gain5 Gain4 Gain3 PGASoft PGAZero Vol6 Vol5 Vol4 Vol3 Vol6 Vol5 Vol4 Vol3 Reserved ADCClkErr CS4245 REV2 REV1 PDN_ADC PDN_DAC MuteDAC DeEmph DAC_M MuteADC HPFFreeze ADC_M MCLK2 MCLK2 Freq2 Freq1 Reserved LOOP Gain2 Gain1 Gain2 Gain1 Sel2 Sel1 ...

Page 41

... The ADC pair will remain in a reset state whenever this bit is set. DS656F2 PART0 REV3 Table 4 REV[2:0] Revision 001 010 B, C0 011 Table 4. Device Revision Reserved PDN_MIC Name Register 03h 04h 07h 08h 0Ah 0Bh Table 5. Freeze-able Bits CS4245 2 1 REV2 REV1 below PDN_ADC PDN_DAC Bit( 5:0 5:0 7:0 7:0 0 REV0 0 PDN 41 ...

Page 42

... Quad-Speed Mode: 100 to 200 kHz sample rates Reserved Table 6. Functional Mode Selection Table 7 and Figures Description Left Justified 24-bit data (default) I² 24-bit data Right-Justified, 16-bit Data Right-Justified, 24-bit Data Table 7. DAC Digital Interface Formats CS4245 MuteDAC DeEmph DAC_M/S 7-9. Format Figure 0 7 ...

Page 43

... ADC_DIF Reserved Mode Single-Speed Mode kHz sample rates Double-Speed Mode 100 kHz sample rates Quad-Speed Mode: 100 to 200 kHz sample rates Reserved Table 9. Functional Mode Selection CS4245 Figure 20, may be implemented for a sample Table 8. NOTE: De-emphasis is available µs Frequency 2 1 MuteADC ...

Page 44

... I² 24-bit data Table 10. ADC Digital Interface Formats “High-Pass Filter and DC Offset Calibration” MCLK1 Reserved Freq0 Table 11 MCLK1 Freq2 MCLK1 Freq1 MCLK1 Freq0 Table 11. MCLK 1 Frequency CS4245 Figure 7 and Figure 8. Format Figure MCLK2 MCLK2 MCLK2 Freq2 Freq1 Freq0 for the appropriate settings ...

Page 45

... MCLK1. DS656F2 MCLK2 Freq2 MCLK2 Freq1 MCLK2 Freq0 Table 12. MCLK 2 Frequency Reserved Reserved AOutSel0 Auxiliary Output Source 0 High Impedance 1 DAC Output 0 PGA Output 1 Reserved Table 13. Auxiliary Output Source Selection 35. CS4245 Table 12 for the appropriate settings Reserved LOOP ASynch Table 13. 45 ...

Page 46

... The 1/8 dB level change will Gain4 Gain3 Gain4 Gain3 Gain[5:0] Setting 101000 -12 dB 000000 0 dB 011000 + PGASoft PGAZero 15. CS4245 Gain2 Gain1 Gain0 Gain2 Gain1 Gain0 Table 14 for ex Sel2 Sel1 Sel0 DS656F2 ...

Page 47

... Sel0 0 Microphone-Level Inputs (+32 dB Gain Enabled Table 16. Analog Input Multiplexer Selection 0Bh Vol4 Vol3 CS4245 Mode Table 16. PGA/ADC Input Line-Level Input Pair 1 Line-Level Input Pair 2 Line-Level Input Pair 3 Line-Level Input Pair 4 Line-Level Input Pair 5 Line-Level Input Pair 6 Reserved 2 1 Vol2 Vol1 0 ...

Page 48

... Binary Code Volume Setting 00000000 00000001 -0.5 dB 00101000 -20 dB 00101001 -20.5 dB 11111110 -127 dB 11111111 -127 Reserved Reserved 18. Table 18. DACZeroCross 0 Changes to affect immediately 1 Zero Cross enabled 0 Soft Ramp enabled 1 Soft Ramp and Zero Cross enabled (default) CS4245 Reserved Reserved Active_H/L Mode 0 DS656F2 ...

Page 49

... INT pin and the status register mask bit is set to 0, the error is masked, meaning that its occurrence will not affect the INT pin or the status register. The bit positions align with the corresponding bits in the Sta- tus register. DS656F2 Reserved ADCClkErr Reserved ADCClkErrM CS4245 DACClkErr ADCOvfl ADCUndrfl DACClkErrM ADCOvflM ADCUndrflM “Interrupt Status - Ad- ...

Page 50

... INT pin becomes active on the removal of the interrupt condition. In Level-Active Mode, the INT pin re- mains active during the interrupt condition Rising edge active 01 - Falling edge active 10 - Level active 11 - Reserved Reserved ADCClkErr1 Reserved ADCClkErr0 CS4245 DACClkErr1 ADCOvfl1 ADCUndrfl1 DACClkErr0 ADCOvfl0 ADCUndrfl0 DS656F2 ...

Page 51

... Units in deci- bels. Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. Gain Drift The change in gain value with temperature. Units in ppm/°C. DS656F2 CS4245 51 ...

Page 52

... Figure 25. DAC Double-Speed Stopband Rejection 52 Figure 22. DAC Single-Speed Transition Band 0.05 0 -0.05 -0. 1 -0.15 -0. 2 -0.25 0 0.05 0.1 0.52 0.53 0.54 0.5 5 Figure 24. DAC Single-Speed Passband Ripple Figure 26. DAC Double-Speed Transition Band CS4245 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 Frequency (normalized to Fs) DS656F2 ...

Page 53

... Figure 30. DAC Quad-Speed Transition Band 0 - -1. 5 0.6 0.65 0.7 0 0.05 Figure 32. DAC Quad-Speed Passband Ripple CS4245 0.1 0.15 0.2 0.25 0.3 0.35 0.4 Frequency (normalized to Fs) 0.4 0.45 0.5 0.55 0.6 0.65 0.7 Frequency(normalized to Fs) 0.1 ...

Page 54

... Figure 38. ADC Double-Speed Stopband Rejection CS4245 0.46 0.48 0.50 0.52 0.54 0.56 0.58 Frequency (norm alized to Fs) 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 Frequency (norm alized to Fs) 0 ...

Page 55

... Figure 44. ADC Quad-Speed Passband Ripple CS4245 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 Frequency (norm alized to Fs) Frequency (norm alized to Fs) Frequency (norm alized to Fs) ...

Page 56

... Symbol θ JA 48-LQFP θ JC CS4245 A A1 MILLIMETERS MIN NOM MAX --- 1.40 1.60 0.05 0.10 0.15 0.17 0.22 0.27 8.70 9.0 BSC 9.30 6.90 7.0 BSC 7 ...

Page 57

... CS4245 Container Order # Tray CS4245-CQZ Tape & Reel CS4245-CQZR Tray CS4245-DQZ Tape & Reel CS4245-DQZR - - CDB4245 Control Port Description and Timing description on page 41. table on page 20. ADC Analog Characteristics table on table on page 7 ...

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