CS42L51-CNZ Cirrus Logic Inc, CS42L51-CNZ Datasheet
CS42L51-CNZ
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CS42L51-CNZ Summary of contents
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... Controls Filters Multibit Oversampling ADC ALC Copyright © Cirrus Logic, Inc. 2006 (All Rights Reserved) CS42L51 + +16 dB MIC Pre-Amplifiers Analog Programmable Gain Amplifier (PGA) Noise Gate for Noise Suppression Programmable Threshold and Attack/Release Rates Programmable, Low Noise MIC Bias Levels Differential MIC Mix for Common Mode Noise Rejection 1 ...
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... Digital Cameras Smart Phones 2 GENERAL DESCRIPTION The CS42L51 is a highly integrated, 24-bit, 96 kHz, low power stereo CODEC. Based on multi-bit, delta-sigma modulation, it allows infinite sample rate adjustment be- tween 4 kHz and 96 kHz. Both the ADC and DAC offer many features suitable for low power, portable system applications ...
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... Noise Gate ............................................................................................................................ 33 4.4 Analog Outputs ............................................................................................................................... 34 4.4.1 De-Emphasis Filter ................................................................................................................ 34 4.4.2 Volume Controls .................................................................................................................... 35 4.4.3 Mono Channel Mixer ............................................................................................................. 35 4.4.4 Beep Generator ..................................................................................................................... 35 4.4.5 Tone Control .......................................................................................................................... 36 4.4.6 Limiter .................................................................................................................................... 36 4.4.7 Line-Level Outputs and Filtering ........................................................................................... 37 4.4.8 On-Chip Charge Pump .......................................................................................................... 38 4.5 Serial Port Clocking ........................................................................................................................ 38 4.5.1 Slave ..................................................................................................................................... 39 4.5.2 Master ................................................................................................................................... 39 DS679F1 CS42L51 3 ...
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... Headphone Amplifier Efficiency ...................................................................................................... 77 7.3 ADC_FILT+ Capacitor Effects on THD+N ...................................................................................... 78 8. EXAMPLE SYSTEM CLOCK FREQUENCIES .................................................................................... 79 8.1 Auto Detect Enabled ....................................................................................................................... 79 8.2 Auto Detect Disabled ...................................................................................................................... 80 9. PCB LAYOUT CONSIDERATIONS ..................................................................................................... 81 9.1 Power Supply, Grounding ............................................................................................................... 81 9.2 QFN Thermal Pad .......................................................................................................................... 81 10. ADC & DAC DIGITAL FILTERS ........................................................................................................ 82 4 CS42L51 DS679F1 ...
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... Figure 33.ADC THD+N vs. Frequency w/Capacitor Effects ...................................................................... 78 Figure 34.ADC Passband Ripple .............................................................................................................. 82 Figure 35.ADC Stopband Rejection .......................................................................................................... 82 Figure 36.ADC Transition Band ................................................................................................................ 82 Figure 37.ADC Transition Band Detail ...................................................................................................... 82 Figure 38.DAC Passband Ripple .............................................................................................................. 82 Figure 39.DAC Stopband .......................................................................................................................... 82 Figure 40.DAC Transition Band ................................................................................................................ 82 Figure 41.DAC Transition Band (Detail) .................................................................................................... 82 DS679F1 CS42L51 5 ...
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... LIST OF TABLES Table 1. I/O Power Rails ............................................................................................................................. 9 Table 2. Hardware Mode Feature Summary ............................................................................................. 27 Table 3. MCLK/LRCK Ratios .................................................................................................................... 39 6 CS42L51 DS679F1 ...
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... Charge Pump Cap Negative Node (Input) - Negative node for the external charge pump capacitor. Negative Voltage From Charge Pump (Output) - Negative voltage rail for the internal analog head- 9 VSS_HP phone section. DS679F1 CS42L51 Pin Description CS42L51 AIN1B 24 AIN1A 23 AFILTB 22 AFILTA 21 AIN2B/BIAS 20 AIN2A 19 MICIN2/BIAS/AIN3B 18 MICIN1/AIN3A 17 7 ...
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... Serial Clock (Input/Output) - Serial clock for the serial audio interface. 32 SDIN Serial Audio Data Input (Input) - Input for two’s complement serial audio data. - Thermal Pad Thermal relief pad for optimized heat dissipation. See 8 CS42L51 “QFN Thermal Pad” on page 81. DS679F1 ...
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... Input/Output SDOUT Input/Output (M/S) SDIN Input DS679F1 Driver - - 1 3.3 V, CMOS/Open Drain - - 1 3.3 V, CMOS 1 3.3 V, CMOS 1 3.3 V, CMOS - Table 1. I/O Power Rails CS42L51 Receiver 1 3 3.3 V, with Hysteresis 1 3.3 V, with Hysteresis 1 3 3 3 3 3 ...
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... Fs R 470 ext This circuitry is intended for applications where the CS42L51 connects directly to an unbalanced output of the device. For internal routing applications please see the DAC Analog Output Characteristics section for loading limitations. Note 5 : Larger capacitors, such as 1.5 µF, improves the charge ...
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... Capacitors must be C0G or equivalent DGND Note 2 : This circuitry is intended for applications where the CS 42L51 connects directly to an unbalanced output of the device . For internal routing applications please see the DAC Analog Output Characteristics section for loading limitations . CS42L51 +1.8V or +2.5V Headphone Out Left & Right R ...
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... Symbol VA VA_HP VD VL Commercial - CNZ T A Automotive - DNZ Symbol VA, VA_HP Analog VD Digital VL Serial/Control Port Interface I (Note IND stg CS42L51 Min Nom Max Units 1.65 1.8 1.89 V 2.37 2.5 2.63 V 1.65 1.8 1.89 V 2.37 2.5 2.63 V 1.65 1.8 1.89 V 2.37 2.5 2. ...
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... ADC 0.75•VA 0.794•VA 0.83•VA PGA (0 dB) 0.129•VA MIC (+16 dB) 0.022•VA MIC (+32 dB ADC - 39 PGA - 50 MIC CS42L51 VA = 1.8 V (nominal) Max Min Typ Max - -80 - - ...
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... PGA to ADC - 78 A-weighted - 74 unweighted - -74 -1 dBFS - 0.1 - ±100 - 352 - 0.74•VA 0.78•VA 0.82•VA ADC 0.75•VA 0.794•VA 0.83•VA PGA (0 dB) 0.129•VA 0.022• ADC 40 - PGA 50 - MIC CS42L51 VA = 1.8 V (nominal) Min Typ Max - -78 - - ...
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... Filter Settling Time 7. Response is clock-dependent and will scale with Fs. Note that the response plots have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs. HPF param- eters are for kHz. DS679F1 (Note 7) to -0.1 dB corner CS42L51 Min Typ Max Unit 0 - ...
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... Refer to Table “Line Output Voltage Characteristics” on (Note 9) Refer to Table “Headphone Output Power Characteristics” 16 Ω kΩ - 0.1 - ±100 (Note 10 (Note 10 CS42L51 = 10 kΩ for the line output 1.8V (nominal) Max Min Typ Max - -78 - -88 ...
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... Refer to Table “Line Output Voltage Characteristics” on (Note 9) Refer to Table “Headphone Output Power Characteristics” 16 Ω kΩ - 0.1 - ±100 (Note 10 (Note 10 CS42L51 = 10 kΩ for the for the headphone output 1.8V (nominal) Max Min Typ Max - -73 ...
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... kΩ (see 2.5V (nominal 1.8V (nominal) Min Typ Max Min - 2.05 - 1.41 1.95 2. (See (Note 11 CS42L51 Figure 3). Typ Max Unit 1. DS679F1 ...
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... High gain settings at certain VA and VA_HP supply levels may 76. reflect the recommended minimum resistance and maximum capacitance re- L AOUTx 51 Ω C 0.022 µF L AGND Figure 3. Headphone Output Test Load CS42L51 = 10 pF (see Figure 3 1.8V (nominal) Min Typ Max - ...
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... SDIN Setup Time Before SCLK Rising Edge SDIN Hold Time After SCLK Rising Edge 20 (Note 12) to -0.05 dB corner corner kHz Fs = 44.1 kHz kHz = 15 pF.) LOAD (Note 14) (Note 15) Quarter-Speed Mode Half-Speed Mode Single-Speed Mode Double-Speed Mode CS42L51 Min Typ Max -0.01 - +0. 0.4780 0 - 0.4996 0.5465 - - 50 ...
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... SDOUT Hold Time After SCLK Rising Edge SDIN Setup Time Before SCLK Rising Edge SDIN Hold Time After SCLK Rising Edge 14. After powering up the CS42L51, RESET should be held low after the power supplies and clocks are settled. 15. See “Example System Clock Frequencies” on page 79 16 ...
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... Repeated Start Start t high t hdst sud t sust low hdd Figure 6. Control Port Timing - I²C CS42L51 Min Max - 100 500 - 4.7 - 4.0 - 4.7 - 4 250 - - 1 - 300 4.7 - 300 3450 , of SCL. fc Stop susp ...
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... RST CS CCLK CDIN DS679F1 ™ CONTROL PORT Symbol f sck t srs t css t csh t scl t sch t dsu t (Note 20 (Note 21 (Note 21 srs css sch scl dsu dh Figure 7. Control Port Timing - SPI Format CS42L51 Min Max Units 0 6.0 MHz µs 1 100 ns - 100 ns t csh ...
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... Low-Level Output Voltage (I OL High-Level Input Voltage Low-Level Input Voltage 24. See “Digital I/O Pin Characteristics” on page 9 24 MICBIAS_LVL[1: MICBIAS_LVL[1: MICBIAS_LVL[1: MICBIAS_LVL[1: kHz (Note 23) 1 kHz (Note 24) Symbol for serial and control port power rails. CS42L51 Min Typ Max - 0.5• ...
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... VA_HP 1.8 2 1.8 2.5 2.5 2 1.8 2 1.8 2.5 2.5 2 1.8 2 1.8 1.66 2.5 2. 1.8 2.77 2.5 3. 1.8 1.66 2.5 2. 1.8 1.66 2.5 2. 1.8 2.77 2.5 3.21 CS42L51 Typical Current (mA (Note 28) ( 0.01 0. 0.01 0. 1.85 2.03 0.03 0 2.07 3.05 0.05 0 2.35 2.03 0. ...
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... In Hardware Mode, a limited feature set may be controlled via stand-alone control pins. 4.1.7 Power Management Two Software Mode control registers provide independent power-down control of the ADC, DAC, PGA, MIC pre-amp and MIC bias, allowing operation in select applications with minimal power consumption. 26 CS42L51 DS679F1 ...
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... Zero Cross (Selectable) Disabled Mix Disabled Beep Disabled Disabled Data Input (PCM) to DAC ADCA = L; ADCB = R ADC PCMA = L; PCMB = R DAC (64xFs)/7 Table 2. Hardware Mode Feature Summary CS42L51 “Recommended Pow- Table 2 shows a list of Stand-Alone Control Note - - - - - - see Section “MCLKDIV2” pin 2 4.5 on page 38 see Section “ ...
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... Boost ADCB_MUTE ADCB_ATT[7:0] 0/-96dB 1dB steps TO SIGNAL PROCESSING ENGINE (SPE) FROM SIGNAL PROCESSING ENGINE (SPE) Figure 8. Analog Input Architecture “Analog Input Characteristics (Commercial - CNZ)” on page 13 73, CS42L51 PGAA_VOL[5:0] ADC_SNGVOL SOFTA PDN_ADCA ZCROSSA +12/-3dB 0.5dB steps AIN1A Multibit AIN2A PGA MUX ...
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... An electrolytic capacitor must be placed such that the positive terminal is positioned relative to the side with the greater bias voltage. The MICBIAS voltage level is controlled by the MICBIAS_LVL[1:0] bits. DS679F1 54. 52. Figure 9. Figure CS42L51 61, “Inter- 10. The two chan- 29 ...
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... Figure 9. MIC Input Mix w/Common Mode Rejection 2.15 V 0.35 V 2. ---------------------------------------------- - = 3. µ 2π 50 kΩ 52, “MIC Control (Address 05h)” on page MICIN1 + 17 Σ MICIN2 + 18 1.25 V 1.25 V Full-Scale Differential Input Level (MICMIX=1) = (AINxA - AINxB RMS Figure 10. Differential Input CS42L51 53. MICBIAS 20 2 AINxA AINxB DS679F1 ...
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... PGAX Control: ALCA, PGAA (Address 0Ah) & ALCB, PGAB (Address 0Bh)” on Controls: page 59, “MIC Control (Address 05h)” on page DS679F1 for the input resistance of each path. 49, “MIC Control (Address 05h)” on page 53 “ADCx 56. 49, “ADCx Input Select, Invert & Mute (Address 07h)” on 53. CS42L51 31 ...
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... ALC) MIN[2:0] below full scale 32 71, MAX[2:0] below full scale RRATE[5:0] ARATE[5:0] Figure 11. ALC CS42L51 70, “ALC Release Rate (Address 1Dh)” on “ALCX & PGAX Control: ALCA, PGAA 59. ADCx_ATT[7:0] and PGAx_VOL[4:0] volume controls should NOT be adjusted manually when ALCx is enabled. MAX[2:0] ...
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... Software “Noise Gate Configuration & Misc. (Address 1Fh)” on page Controls: page 54. DS679F1 “Differential Inputs” on page Output (dB) -52 dB -64 dB -80 dB -96 -40 THRESH[2:0] Figure 12. Noise Gate Attenuation CS42L51 29), enable the NG_ALL bit 72, “ADC Control (Address 06h)” on Input (dB) 33 ...
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... BASS[3:0] INV_DACB TREB[3:0] DAC_SNGVOL +12.0dB/-10.5dB AMUTE 1.5dB steps VOL Figure 13. Output Architecture 14. The de-emphasis feature is included to accommodate audio recordings 58. Setting LO HI De-Emphasis Applied CS42L51 DATA_SEL[1:0] PDN_DACA PDN_DACB HP_GAIN[2:0] Headphone Switched Amp - GND Capacitor DAC 01 Centered and Filter 00 Charge Pump CHRG_FREQ[3:0] ...
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... Software (Address 13h)” on page Controls: DS679F1 dB T1=50 µs 0dB µ Frequency 3.183 kHz 10.61 kHz Figure 14. De-Emphasis Curve 57. 67. 63, “Beep Configuration & Tone Configuration (Address 14h)” on page 64 CS42L51 61, “PCMX 62, “AOUTx Vol- 66, “DAC Output Control 62, “Beep Off Time & Volume 35 ...
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... Software “Limiter Release Rate Register (Address 1Ah)” on page Controls: 1Bh)” on page 36 OFFTIME[2:0] Figure 15. Beep Configuration Options 65. 70, “DAC Control (Address 09h)” on page 58 CS42L51 ... 69, “Limiter Attack Rate Register (Address DS679F1 ...
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... RRATE[5:0] Figure 16. Peak Detect & Limiter “Typical Connection Diagram (Software Mode)” on page 10 11, is required on the analog outputs. This allows the 57, “AOUTx Volume Control: AOUTA (Address 16h) 66. CS42L51 AOUTx_VOL[7:0] volume control should NOT be adjusted manually when Limiter is enabled. CUSH[2:0] and the “ ...
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... Pump Frequency (Address 21h)” on page “MIC Power Control & Speed Control (Address 03h)” on page (Address 09h)” on page 58. Pin 47 kΩ Pull-down “SDOUT, M/S” pin 29 47 kΩ Pull-up “MCLKDIV2” pin 2 CS42L51 for the recommended capacitor 74. 50, “DAC Control Setting Selection Slave Master ...
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... Speed MCLKDIV2 Single ÷ 2 Speed Half ÷ 4 Speed Quarter ÷ 8 Speed Figure 17. Master Mode Timing CS42L51 SSM DSM 128, 192, 256, 384, 128, 192, 256, 384 512, 768 256, 384, 512*, 768* 128, 192, 256*, 384 LRCK Output (Equal to Fs) 10 ...
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... Hardware Control: “I²S/LJ” pin 3 LRCK L eft SCLK SDIN AOUTA / AINxA 40 Transmitting Device #2 SDOUT 3ST_SP SCLK/LRCK Receiving Device Figure 18. Tri-State Serial Port 52. Setting LO Left-Justified Interface HI I²S Interface AOUTB / AINxB Figure 19. I²S Format CS42L51 “Switching Specifications - Se- Selection DS679F1 MSB ...
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... Bring RESET low if the analog or digital supplies drop below the recommended operating condition to prevent power glitch related issues. DS679F1 Figure 20. Left-Justified Format Figure 21. Right-Justified Format (DAC only) 43 valid write sequence to the control port is not made within approximately CS42L51 MSB AOUTB / AINxB AOUTB Figure 22 on page 42 ...
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... Audio signal generated per control port or stand- ERROR: MCLK/LRCK ratio change alone settings. ERROR: MCLK removed Analog Output Freeze 1. Aout bias = last audio sample. 2. DAC Modulators stop operation. 3. Audible pops. Figure 22. Initialization Flowchart CS42L51 Standby Mode Yes 1. No audio signal generated. 2. Control Port Registers retain settings Valid ...
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... AD0 bit address state. 4.10.1 SPI Control In Software Mode the CS42L51 chip-select signal, CCLK is the control port bit clock (input into the CS42L51 from the microcontroller), CDIN is the input data line from the microcontroller. Data is clocked in on the rising edge of CCLK. The CODEC will only support write operations. Read request will be ig- nored ...
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... INCR ACK ACK Figure 24. Control Port Timing, I²C Write STOP MAP BYTE CHIP ADDRESS (READ INCR ACK START Figure 25. Control Port Timing, I²C Read CS42L51 CS42L51 DATA +1 DATA + ACK ACK DATA DATA +1 DATA + AD0 ACK ACK ACK from STOP NO STOP DS679F1 ...
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... The device has MAP auto-increment capability enabled by the INCR bit (the MSB) of the MAP. If INCR is set to 0, MAP will stay constant for successive I²C writes or reads and SPI writes. If INCR is set to 1, MAP will auto-increment after each byte is read or written, allowing block reads or writes of successive registers. DS679F1 CS42L51 45 ...
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... FREEZE Reserved Reserved PGAA DIS VOL4 Reserved PGAB DIS VOL4 ADCA_ ADCA_ ADCA_ ATT6 ATT5 ATT4 ADCB_ ADCB_ ADCB_ ATT6 ATT5 ATT4 CS42L51 Chip_ID0 Rev_ID2 Rev_ID1 PDN_ADCB PDN_ADCA PDN_MICA PDN_ MICBIAS ADC_I²S/LJ DIGMIX MICBIAS_ MICB_ LVL1 LVL0 BOOST SOFTB ZCROSSB ...
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... TREB_CF0 TREB2 TREB1 TREB0 AOUTA_ AOUTA_ VOL6 VOL5 VOL4 AOUTB_ AOUTB_ VOL6 VOL5 VOL4 PCMB1 PCMB0 MAX1 MAX0 CUSH2 CS42L51 ADCMIXA ADCMIXA ADCMIXA VOL3 VOL2 VOL1 ADCMIXB ADCMIXB ADCMIXB VOL3 VOL2 VOL1 PCMMIXA PCMMIXA VOL3 VOL2 VOL1 PCMMIXB PCMMIXB VOL3 VOL2 ...
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... LIM_ARATE5 LIM_ARATE4 LIM_ARATE3 LIM_ARATE2 LIM_ARATE1 LIM_ARATE0 ALC_ARATE AALC_RATE ALC_ARATE ALC_RRATE ALC_RRATE ALC_RRATE MAX1 MAX0 MIN2 NG_BOOST THRESH2 THRESH1 SPEB_OVFL SPEA_OVFL PCMA_OVFL PCMB_OVFL ADCA_OVFL ADCB_OVFL CHRG_ CHRG_ FREQ2 FREQ1 FREQ0 CS42L51 LIM_RRATE LIM_RRATE ALC_ARATE ALC_ARATE ALC_RRATE ALC_RRATE Reserved MIN1 MIN0 THRESH0 NGDELAY1 ...
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... Chip_ID2 Chip I.D. (Chip_ID[4:0]) Default: 11011 Function: I.D. code for the CS42L51. Permanently set to 11011. Chip Revision (Rev_ID[2:0]) Default: 001 Function: CS42L51 revision level. Revision B is coded as 001. Revision A is coded as 000. 6.2 Power Control 1 (Address 02h Reserved PDN_DACB PDN_DACA Notes: 1 ...
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... When AUTO is enabled, the MCLK/LRCK ratio must be implemented according to SPEED[1:0] bits are ignored when this bit is enabled. Speed is determined by the MCLK/LRCK ratio. 50 above. for the required settings 3-ST_SP PDN_MICB CS42L51 Power Control 1 on page PDN_MICA PDN_MICBIAS MCLKDIV2 Table 3 on page 39. The ...
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... Function: When enabled, the microphone bias circuit will power-down state. MCLK Divide By 2 (MCLKDIV2) Default Disabled 1 - Divide by 2 Function: Divides the input MCLK by 2 prior to all internal circuitry. This bit is ignored when the AUTO bit is disabled in Slave Mode. DS679F1 above). CS42L51 51 ...
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... Selects the digital interface format used for the data in on SDIN. The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital Interface Format and the options are detailed in the section “Digital Interface Formats” on page DAC_DIF1 DAC_DIF0 Description 40. CS42L51 ADC_I²S/LJ DIGMIX MICMIX Figure 20 on page page page page 41 ...
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... ALC_ENB control register is ignored. DS679F1 Mix Selected No Mix: ADC to ADC serial port, SDOUT data. No Mix: SDIN data to ADC serial port, SDOUT data. Mix: ADC + SDIN data to ADC serial port, SDOUT data. No Mix: ADC to ADC serial port, SDOUT data. Reserved CS42L51 MICB_BOOST MICA_BOOST 53 ...
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... When this bit is set, the internal high-pass filter will be enabled for ADCx. When set to ‘0’, the high-pass filter will be disabled. For DC measurements, this bit must be cleared to ‘0’. tics” on page 15 SOFTB CS42L51 ZCROSSB SOFTA ZCROSSA See “ADC Digital Filter Characteris- DS679F1 ...
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... Analog PGA Volume (PGAx_VOL[4:0]) Volume changes immediately. Volume changes at next zero cross time. Volume changes in 0.5 dB steps. Volume changes in 0.5 dB steps at every signal zero-cross. CS42L51 15. Digital Attenuator (ADCx_ATT[7:0]) Volume changes immediately. Volume changes immediately. Change volume in 0.125 dB steps. Change volume in 0.125 dB steps. ...
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... INV_ADCB Selected Path to ADC AIN1x-->PGAx AIN2x-->PGAx AIN3x/MICINx-->PGAx AIN3x/MICINx-->Pre-Amp (+16/+32 dB Gain) AIN1x AIN2x AIN3x/MICINx Reserved Figure 26. MUX PGA +16 Decoder AINx_MUX[1:0] PDN_PGAx Figure 26. AIN & PGA Selection CS42L51 2 1 INV_ADCA ADCB_MUTE ADCA_MUTE -->PGAx AIN1x AIN2x ADC MUX AIN3x DS679F1 0 ...
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... DACX Channel Mute (DACX_MUTE) Default Disabled 1 - Enabled Function: The output of channel x DAC will mute when enabled. The muting function is affected by the DACx Soft and Zero Cross bits (DACx_SZC[1:0]). DS679F1 DAC_ INV_PCMB SNGVOL CS42L51 INV_PCMA DACB_MUTE DACA_MUTE “Line Output Voltage Characteris- 19. 57 ...
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... Enables the digital filter to apply the standard 15µs/50µs digital de-emphasis filter response for a sample rate of 44.1 kHz. Analog Output Auto MUTE (AMUTE) Default Auto Mute Disabled 1 - Auto Mute Enabled Function: Enables (or disables) Automatic Mute of the analog outputs after 8192 “0” samples on each digital input channel Reserved DEEMPH CS42L51 AMUTE DAC_SZC1 DAC_SZC0 DS679F1 ...
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... Function: Overrides the SOFTx bit setting for the ADC. When this bit is set, the ALC attack rate in the PGA will not be dictated by the soft ramp setting. ALC volume-level changes will take effect in one step. DS679F1 PGAX_VOL4 PGAX_VOL3 CS42L51 PGAX_VOL2 PGAX_VOL1 PGAX_VOL0 59 ...
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... Volume Setting +12 dB ··· ··· -0 ··· ADCx_ATT4 ADCx_ATT3 Volume Setting 0 dB ··· ··· -96 dB ··· -96 dB CS42L51 ADCx_ATT2 ADCx_ATT1 ADCx_ATT0 DS679F1 ...
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... The level of the ADCX input to the output mixer can be adjusted in 0.5 dB increments as dictated by the DACX Soft and Zero Cross bits (DACX_SZC[1:0]) from +12 to -51.5 dB. Levels are decoded as shown in the table above. DS679F1 Volume Setting +12.0 dB ··· -0.5 dB -1.0 dB ··· -51.5 dB CS42L51 ...
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... Fs = 12, 24 kHz 0000 260.87 Hz 0001 521.74 Hz 0010 585.37 Hz 0011 666.67 Hz 0100 705. PCMMIXx_ PCMMIXx_ VOL4 VOL3 Volume Setting +12.0 dB ··· -0.5 dB -1.0 dB ··· -51 FREQ0 ONTIME3 Pitch CS42L51 PCMMIXx_ PCMMIXx_ PCMMIXx_ VOL2 VOL1 VOL0 ONTIME2 ONTIME1 ONTIME0 DS679F1 ...
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... Note: The DATA_SEL[1:0] bits in reg09h must be set to ‘01’b to enable function control in this register. Beep Off Time (OFFTIME[2:0]) Default: 000 OFFTIME[2:0] Off Time Fs = 12, 24 kHz 000 1.23 s 001 2.58 s 010 3.90 s 011 5.20 s 100 6.60 s 101 8.05 s DS679F1 Pitch Time 86 ms ··· 5 BPVOL4 BPVOL3 CS42L51 Figure 15 on Figure BPVOL2 BPVOL1 BPVOL0 63 ...
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... Figure 15 on page 36 Beep (BEEP) Default Disabled 1 - Enabled Function: 64 9.35 s Volume Setting +12.0 dB ··· ··· -50 dB for single-, multiple- and continuous-beep configurations using the REPEAT TREB_CF1 TREB_CF0 for a description of each configuration option. CS42L51 BASS_CF1 BASS_CF0 TC_EN DS679F1 ...
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... Default: 1000 dB (No Treble Gain) Binary Code 0000 ··· 0111 1000 1001 ··· 1111 DS679F1 Figure 15 on page TREB0 BASS3 Gain Setting +12.0 dB ··· +1 -1.5 dB ··· -10.5 dB CS42L51 for a description of each con BASS2 BASS1 BASS0 65 ...
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... When the limiter is enabled, the AOUT Volume is automatically controlled and should not be ad- justed manually. Alternative volume control may be achieved using the PCMMIXx_VOL[6:0] bits. 66 Gain Setting +12.0 dB ··· +1 -1.5 dB ··· -10 Volume Setting +12.0 dB ··· -0.5 dB -1.0 dB ··· -102 dB ··· -102 dB CS42L51 DS679F1 ...
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... Sets the maximum level, below full scale, at which to limit and attenuate the output signal at the attack rate. Bass, Treble and digital gain settings that boost the signal beyond the maximum threshold may trigger an attack. DS679F1 PCMB0 ADCA1 AOUTB ADCB[1: ----------- - CUSH2 CUSH1 CS42L51 ADCA0 ADCB1 ADCB0 CUSH0 LIM_SRDIS LIM_ZCDIS 67 ...
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... Note: This bit is ignored when the zero-cross function is enabled (i.e. when DAC_SZC[1:0] = ‘01’b or ‘11’b.) Limiter Zero Cross Disable (LIM_ZCDIS) Default Off Function: Overrides the DAC_SZC setting. When this bit is set, the Limiter attack and release rate will not be dictated by the zero-cross setting. 68 CS42L51 DS679F1 ...
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... AOUTx_VOL[7:0] setting. The limiter release rate is user selectable but is also a function of the sampling frequency, Fs, and the DAC_SZC setting unless the disable bit is enabled. DS679F1 RRATE4 RRATE3 Release Time Fastest Release ··· Slowest Release CS42L51 RRATE2 RRATE1 RRATE0 69 ...
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... The limiter attack rate is user-selectable but is also a function of the sampling frequency, Fs, and the SOFTx & ZCROSSx bit settings unless the disable bit for each function is enabled ARATE4 ARATE3 Attack Time Fastest Attack ··· Slowest Attack Attack Time Fastest Attack ··· Slowest Attack CS42L51 ARATE2 ARATE1 ARATE0 DS679F1 ...
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... Sets the maximum level, relative to full scale, at which to limit and attenuate the input signal at the attack rate. Minimum Threshold (MIN[2:0]) Default: 000 Threshold MIN[2:0] Setting (dB) 000 0 001 -3 010 -6 DS679F1 Release Time Fastest Release ··· Slowest Release MIN2 MIN1 CS42L51 MIN0 Reserved Reserved 71 ...
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... Minimum Setting THRESH[2:0] (NG_BOOST = ‘0’b) 000 001 010 011 100 101 110 111 THRESH2 THRESH1 Minimum Setting (NG_BOOST = ‘1’b) -64 dB -34 dB -67 dB -37 dB -70 dB -40 dB -73 dB -43 dB -76 dB -46 dB -82 dB -52 dB Reserved -58 dB Reserved -64 dB CS42L51 THRESH0 NGDELAY1 NGDELAY0 DS679F1 ...
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... PCMX Overflow (PCMX_OVFL) Default: 0 Function: Indicates a digital overflow condition within the data path of the PCM mix. ADC Overflow (ADCX_OVFL) Default = 0 Function: Indicates that there is an over-range condition anywhere in the CS42L51 ADC signal path of each of the associated ADC’s. DS679F1 SPEB_OVFL PCMA_OVFL PCMB_OVFL ADCA_OVFL “ ...
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... Alters the clocking frequency of the charge pump in 1/(N+2) fractions of the DAC oversampling rate, 128Fs, should the switching frequency interfere with other system frequencies such as those in the AM radio band. Note: Distortion performance may be affected CHRG_FREQ Reserved 1 0 Frequency 64xFs ---------------- - CS42L51 Reserved Reserved Reserved DS679F1 ...
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... W 40m 50m 60m 70m 80m W CS42L51 G = 0.6047 G = 0.7099 G = 0.8399 G = 1.0000 G = 1.1430 Legend NOTE: Graph shows the out- put power per channel (i.e. Output Power = 23 mW into single 16 Ω and 46 mW into stereo 16 Ω with THD dB). ...
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... W 30m 35m 40m 45m 50m 55m 60m W CS42L51 G = 0.6047 G = 0.7099 G = 0.8399 G = 1.0000 G = 1.1430 Legend NOTE: Graph shows the out- put power per channel (i.e. Output Power = 22 mW into single 32 Ω and 44 mW into stereo 32 Ω with THD dB). ...
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... Input test signal is a 997 Hz sine wave; Power Consumption Mode 6 - Stereo Playback w/16 Ω load. HP_GAIN = 1.1430. Best efficiency is realized when the amplifier outputs maximum power. VA_HP = VA = 1.8 V Figure 31. Power Dissipation vs. Output Power into Stereo 16 Ω VA_HP = VA = 1.8 V Figure 32. Power Dissipation vs. Output Power into Stereo 16 Ω (Log Detail) DS679F1 CS42L51 77 ...
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... CDB42L51 using an Audio Precision analyzer. -60 -64 -68 - -84 -88 -92 -96 -100 20 50 100 200 Figure 33. ADC THD+N vs. Frequency w/Capacitor Effects 78 shows the THD+N versus frequency for the ADC analog input. Plots were tak- 500 10k 20k Hz CS42L51 1 µF 10 µF 22 µF Legend – Capacitor Value on ADC_FILT+ DS679F1 ...
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... MCLK (MHz) 256x 384x 8.1920 12.2880 11.2896 16.9344 12.2880 18.4320 MCLK (MHz) 128x 192x 8.1920 12.2880 11.2896 16.9344 12.2880 18.4320 CS42L51 2048x* 3072x* 16.3840 24.5760 22.5792 33.8688 24.5760 36.8640 1024x* 1536x* 16.3840 24.5760 22.5792 33.8688 24.5760 36.8640 512x* 768x* 16.3840 24 ...
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... MCLK (MHz) 256x 384x 8.1920 12.2880 11.2896 16.9344 12.2880 18.4320 MCLK (MHz) 128x 192x 8.1920 12.2880 11.2896 16.9344 12.2880 18.4320 CS42L51 2048x 3072x 16.3840 24.5760 22.5792 33.8688 24.5760 36.8640 1024x 1536x 16.3840 24.5760 22.5792 33.8688 24.5760 36.8640 512x 768x 16.3840 24 ...
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... QFN Thermal Pad The CS42L51 is available in a compact QFN package. The under side of the QFN package reveals a large metal pad that serves as a thermal relief to provide for maximum heat dissipation. This pad must mate with an equally dimensioned copper pad on the PCB and must be electrically connected to ground. A series of vias should be used to connect this copper pad to one or more larger ground planes on other PCB layers ...
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... DAC DIGITAL FILTERS Figure 34. ADC Passband Ripple Figure 36. ADC Transition Band Figure 38. DAC Passband Ripple Figure 40. DAC Transition Band 82 Figure 35. ADC Stopband Rejection Figure 37. ADC Transition Band Detail Figure 39. DAC Stopband Figure 41. DAC Transition Band (Detail) CS42L51 DS679F1 ...
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... The deviation from the nominal full-scale analog output for a full-scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/°C. Offset Error The deviation of the mid-scale transition (111...111 to 000...000) from the ideal. Units in mV. DS679F1 CS42L51 83 ...
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... JEDEC #: MO-220 Controlling Dimension is Millimeters. Symbol 2 Layer Board 4 Layer Board CS42L51 b e Pin #1 Corner L D2 Bottom View MILLIMETERS NOM MAX -- 1.00 -- 0.05 0.23 0.28 5.00 BSC 3.30 3.35 5.00 BSC 3 ...
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... Philips Semiconductor, The I²C-Bus Specification: Version 2.1, January 2000. http://www.semiconductors.philips.com DS679F1 Package Pb-Free Grade Temp Range Commercial -10 to +70° C 32L-QFN Yes Automotive -40 to +85° CS42L51 Container Order # Rail CS42L51-CNZ Tape & Reel CS42L51-CNZR Rail CS42L51-DNZ Tape & Reel CS42L51-DNZR - - CDB42L51 - - CRD42L51 85 ...
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... Mix (DIGMIX)” on page “Zero Cross” on page “Beep Off Time (OFFTIME[2:0])” on page “Beep (BEEP)” on page 64. “Noise Gate Boost (NG_BOOST) and Threshold (THRESH[3:0])” on “Charge Pump Frequency (CHRG_FREQ[3:0])” on CS42L51 10. “Typical Connection 11. and “Analog 19. 20. “Switching Specifications - Serial Port” on “ ...
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... V IH “Automatic Level Control (ALC)” on page 77. “MIC Control (Address 05h)” on page CS42L51 12. 12. “Analog Input Characteris- and 14. 14. 15. “Analog Output Characteristics (Commer- 17. from table in section s(SDO-SK) “ ...
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... Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. I² registered trademark of Philips Semiconductor. SPI is a trademark of Motorola, Inc. 88 www.cirrus.com. CS42L51 DS679F1 ...