CS42516-CQZ Cirrus Logic Inc, CS42516-CQZ Datasheet - Page 47

• Manufacturer Part Number: CS42516-CQZ
• Description: IC CODEC S/PDIF RCVR 64LQFP
• Manufacturer: Cirrus Logic Inc
• Type: General Purposer

Specifications of CS42516-CQZ

• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 6
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 114 / 110
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 3.13 V ~ 5.25 V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Audio Codec Type: Stereo
• No. Of Adcs: 2
• No. Of Dacs: 6
• No. Of Input Channels: 2
• No. Of Output Channels: 6
• Adc / Dac Resolution: 24bit
• Adcs / Dacs Signal To Noise Ratio: 110dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1502 - BOARD EVAL FOR CS42518 CODEC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 598-1035

DS583F1
6.3
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
PDN_RCVR1 PDN_RCVR0
7
Power Control (address 02h)
POWER DOWN RECEIVER (PDN_RCVRX)
POWER DOWN ADC (PDN_ADC)
POWER DOWN RESERVE TEST (PDN_RSVD)
POWER DOWN DAC PAIRS (PDN_DACX)
POWER DOWN (PDN)
Default = 10
00 - Receiver and PLL in normal operational mode.
01 - Receiver and PLL held in a reset state. Equivalent to setting 11.
10 - Reserved.
11 - Receiver and PLL held in a reset state. Equivalent to setting 01.
Function:
Default = 0
Function:
Default = 0
Function:
Default = 0
Function:
Default = 1
Function:
Places the S/PDIF receiver and PLL in a reset state. It is advised that any change of these bits be
made while the DACs are muted or the power-down bit (PDN) is enabled to eliminate the possibility
of audible artifacts.
It should be noted that, for Revision C compatibility, PDN_RCVR1 may be set to ‘0’ and receiver op-
eration may be controlled with the PDN_RCVR0 bit.
When enabled the stereo analog to digital converter will remain in a reset state. It is advised that any
change of this bit be made while the DACs are muted or the power-down bit (PDN) is enabled to elim-
inate the possibility of audible artifacts.
This bit is a reserved power down bit used for test purposes only. For proper operation, this bit must
be set to ‘1’.
When enabled the respective DAC channel pair x (AOUTAx and AOUTBx) will remain in a reset state.
The entire device will enter a low-power state when this function is enabled, and the contents of the
control registers are retained in this mode. The power-down bit defaults to ‘enabled’ on power-up and
must be disabled before normal operation can occur.
6
PDN_ADC
5
Reserved
4
PDN_DAC3
3
PDN_DAC2
2
PDN_DAC1
1
CS42516
PDN
0
47